a26f067fea
Changes since v8: - Corrected license identifiers Changes since v7: - Add padding to struct rogue_fwif_ccb_ctl to place read and write offsets in different cache lines Changes since v5: - Split up header commit due to size - Add BRN 71242 to device info Changes since v4: - Add FW header device info Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Donald Robson <donald.robson@imgtec.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/aa681533a02bd2d46af17a6a6010f4d6048fbb0a.1700668843.git.donald.robson@imgtec.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
374 lines
10 KiB
C
374 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_ROGUE_FWIF_CLIENT_H
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#define PVR_ROGUE_FWIF_CLIENT_H
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#include <linux/bits.h>
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include "pvr_rogue_fwif_shared.h"
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/*
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* Page size used for Parameter Management.
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*/
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#define ROGUE_PM_PAGE_SIZE SZ_4K
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/*
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* Minimum/Maximum PB size.
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*
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* Base page size is dependent on core:
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* S6/S6XT/S7 = 50 pages
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* S8XE = 40 pages
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* S8XE with BRN66011 fixed = 25 pages
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*
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* Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
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* IF_PM_PREALLOC(NUM_TE_PIPES*16K + NUM_VCE_PIPES*16K)
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*
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* Maximum PB size must ensure that no PM address space can be fully used,
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* because if the full address space was used it would wrap and corrupt itself.
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* Since there are two freelists (local is always minimum sized) this can be
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* described as following three conditions being met:
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*
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* (Minimum PB + Maximum PB) < ALIST PM address space size (16GB)
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* (Minimum PB + Maximum PB) < TE PM address space size (16GB) / NUM_TE_PIPES
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* (Minimum PB + Maximum PB) < VCE PM address space size (16GB) / NUM_VCE_PIPES
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*
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* Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit
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* of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
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* value of 2GB. This is far more than any current applications use.
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*/
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#define ROGUE_PM_MAX_FREELIST_SIZE SZ_2G
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/*
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* Flags supported by the geometry DM command i.e. &struct rogue_fwif_cmd_geom.
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*/
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#define ROGUE_GEOM_FLAGS_FIRSTKICK BIT_MASK(0)
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#define ROGUE_GEOM_FLAGS_LASTKICK BIT_MASK(1)
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/* Use single core in a multi core setup. */
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#define ROGUE_GEOM_FLAGS_SINGLE_CORE BIT_MASK(3)
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/*
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* Flags supported by the fragment DM command i.e. &struct rogue_fwif_cmd_frag.
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*/
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/* Use single core in a multi core setup. */
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#define ROGUE_FRAG_FLAGS_SINGLE_CORE BIT_MASK(3)
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/* Indicates whether this render produces visibility results. */
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#define ROGUE_FRAG_FLAGS_GET_VIS_RESULTS BIT_MASK(5)
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/* Indicates whether a depth buffer is present. */
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#define ROGUE_FRAG_FLAGS_DEPTHBUFFER BIT_MASK(7)
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/* Indicates whether a stencil buffer is present. */
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#define ROGUE_FRAG_FLAGS_STENCILBUFFER BIT_MASK(8)
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/* Disable pixel merging for this render. */
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#define ROGUE_FRAG_FLAGS_DISABLE_PIXELMERGE BIT_MASK(15)
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/* Indicates whether a scratch buffer is present. */
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#define ROGUE_FRAG_FLAGS_SCRATCHBUFFER BIT_MASK(19)
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/* Disallow compute overlapped with this render. */
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#define ROGUE_FRAG_FLAGS_PREVENT_CDM_OVERLAP BIT_MASK(26)
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/*
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* Flags supported by the compute DM command i.e. &struct rogue_fwif_cmd_compute.
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*/
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#define ROGUE_COMPUTE_FLAG_PREVENT_ALL_OVERLAP BIT_MASK(2)
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/*!< Use single core in a multi core setup. */
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#define ROGUE_COMPUTE_FLAG_SINGLE_CORE BIT_MASK(5)
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/*
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* Flags supported by the transfer DM command i.e. &struct rogue_fwif_cmd_transfer.
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*/
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/*!< Use single core in a multi core setup. */
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#define ROGUE_TRANSFER_FLAGS_SINGLE_CORE BIT_MASK(1)
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/*
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************************************************
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* Parameter/HWRTData control structures.
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************************************************
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*/
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/*
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* Configuration registers which need to be loaded by the firmware before a geometry
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* job can be started.
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*/
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struct rogue_fwif_geom_regs {
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u64 vdm_ctrl_stream_base;
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u64 tpu_border_colour_table;
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/* Only used when feature VDM_DRAWINDIRECT present. */
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u64 vdm_draw_indirect0;
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/* Only used when feature VDM_DRAWINDIRECT present. */
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u32 vdm_draw_indirect1;
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u32 ppp_ctrl;
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u32 te_psg;
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/* Only used when BRN 49927 present. */
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u32 tpu;
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u32 vdm_context_resume_task0_size;
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/* Only used when feature VDM_OBJECT_LEVEL_LLS present. */
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u32 vdm_context_resume_task3_size;
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/* Only used when BRN 56279 or BRN 67381 present. */
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u32 pds_ctrl;
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u32 view_idx;
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/* Only used when feature TESSELLATION present */
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u32 pds_coeff_free_prog;
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u32 padding;
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};
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/* Only used when BRN 44455 or BRN 63027 present. */
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struct rogue_fwif_dummy_rgnhdr_init_geom_regs {
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u64 te_psgregion_addr;
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};
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/*
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* Represents a geometry command that can be used to tile a whole scene's objects as
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* per TA behavior.
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*/
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struct rogue_fwif_cmd_geom {
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/*
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* rogue_fwif_cmd_geom_frag_shared field must always be at the beginning of the
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* struct.
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*
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* The command struct (rogue_fwif_cmd_geom) is shared between Client and
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* Firmware. Kernel is unable to perform read/write operations on the
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* command struct, the SHARED region is the only exception from this rule.
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* This region must be the first member so that Kernel can easily access it.
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* For more info, see rogue_fwif_cmd_geom_frag_shared definition.
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*/
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struct rogue_fwif_cmd_geom_frag_shared cmd_shared;
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struct rogue_fwif_geom_regs regs __aligned(8);
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u32 flags __aligned(8);
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/*
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* Holds the geometry/fragment fence value to allow the fragment partial render command
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* to go through.
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*/
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struct rogue_fwif_ufo partial_render_geom_frag_fence;
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/* Only used when BRN 44455 or BRN 63027 present. */
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struct rogue_fwif_dummy_rgnhdr_init_geom_regs dummy_rgnhdr_init_geom_regs __aligned(8);
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/* Only used when BRN 61484 or BRN 66333 present. */
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u32 brn61484_66333_live_rt;
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u32 padding;
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};
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/*
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* Configuration registers which need to be loaded by the firmware before ISP
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* can be started.
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*/
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struct rogue_fwif_frag_regs {
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u32 usc_pixel_output_ctrl;
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#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
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u32 usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
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u32 isp_bgobjdepth;
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u32 isp_bgobjvals;
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u32 isp_aa;
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/* Only used when feature S7_TOP_INFRASTRUCTURE present. */
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u32 isp_xtp_pipe_enable;
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u32 isp_ctl;
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/* Only used when BRN 49927 present. */
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u32 tpu;
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u32 event_pixel_pds_info;
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/* Only used when feature CLUSTER_GROUPING present. */
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u32 pixel_phantom;
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u32 view_idx;
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u32 event_pixel_pds_data;
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/* Only used when BRN 65101 present. */
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u32 brn65101_event_pixel_pds_data;
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/* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */
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u32 isp_oclqry_stride;
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/* Only used when feature ZLS_SUBTILE present. */
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u32 isp_zls_pixels;
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/* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */
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u32 rgx_cr_blackpearl_fix;
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/* All values below the ALIGN(8) must be 64 bit. */
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aligned_u64 isp_scissor_base;
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u64 isp_dbias_base;
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u64 isp_oclqry_base;
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u64 isp_zlsctl;
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u64 isp_zload_store_base;
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u64 isp_stencil_load_store_base;
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/*
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* Only used when feature FBCDC_ALGORITHM present and value < 3 or feature
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* FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must
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* not be present.
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*/
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u64 fb_cdc_zls;
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#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U
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u64 pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS];
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u64 tpu_border_colour_table;
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u64 pds_bgnd[3U];
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/* Only used when BRN 65101 present. */
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u64 pds_bgnd_brn65101[3U];
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u64 pds_pr_bgnd[3U];
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/* Only used when BRN 62850 or 62865 present. */
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u64 isp_dummy_stencil_store_base;
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/* Only used when BRN 66193 present. */
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u64 isp_dummy_depth_store_base;
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/* Only used when BRN 67182 present. */
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u32 rgnhdr_single_rt_size;
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/* Only used when BRN 67182 present. */
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u32 rgnhdr_scratch_offset;
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};
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struct rogue_fwif_cmd_frag {
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struct rogue_fwif_cmd_geom_frag_shared cmd_shared __aligned(8);
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struct rogue_fwif_frag_regs regs __aligned(8);
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/* command control flags. */
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u32 flags;
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/* Stride IN BYTES for Z-Buffer in case of RTAs. */
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u32 zls_stride;
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/* Stride IN BYTES for S-Buffer in case of RTAs. */
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u32 sls_stride;
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/* Only used if feature GPU_MULTICORE_SUPPORT present. */
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u32 execute_count;
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};
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/*
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* Configuration registers which need to be loaded by the firmware before CDM
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* can be started.
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*/
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struct rogue_fwif_compute_regs {
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u64 tpu_border_colour_table;
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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u64 cdm_cb_queue;
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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u64 cdm_cb_base;
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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u64 cdm_cb;
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/* Only used when feature CDM_USER_MODE_QUEUE is not present. */
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u64 cdm_ctrl_stream_base;
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u64 cdm_context_state_base_addr;
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/* Only used when BRN 49927 is present. */
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u32 tpu;
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u32 cdm_resume_pds1;
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/* Only used when feature COMPUTE_MORTON_CAPABLE present. */
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u32 cdm_item;
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/* Only used when feature CLUSTER_GROUPING present. */
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u32 compute_cluster;
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/* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */
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u32 tpu_tag_cdm_ctrl;
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u32 padding;
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};
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struct rogue_fwif_cmd_compute {
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/* Common command attributes */
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struct rogue_fwif_cmd_common common __aligned(8);
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/* CDM registers */
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struct rogue_fwif_compute_regs regs;
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/* Control flags */
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u32 flags __aligned(8);
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/* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */
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u32 num_temp_regions;
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/* Only used when feature CDM_USER_MODE_QUEUE present. */
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u32 stream_start_offset;
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/* Only used when feature GPU_MULTICORE_SUPPORT present. */
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u32 execute_count;
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};
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struct rogue_fwif_transfer_regs {
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/*
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* All 32 bit values should be added in the top section. This then requires only a
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* single RGXFW_ALIGN to align all the 64 bit values in the second section.
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*/
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u32 isp_bgobjvals;
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u32 usc_pixel_output_ctrl;
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u32 usc_clear_register0;
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u32 usc_clear_register1;
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u32 usc_clear_register2;
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u32 usc_clear_register3;
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u32 isp_mtile_size;
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u32 isp_render_origin;
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u32 isp_ctl;
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/* Only used when feature S7_TOP_INFRASTRUCTURE present. */
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u32 isp_xtp_pipe_enable;
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u32 isp_aa;
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u32 event_pixel_pds_info;
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u32 event_pixel_pds_code;
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u32 event_pixel_pds_data;
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u32 isp_render;
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u32 isp_rgn;
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/* Only used when feature GPU_MULTICORE_SUPPORT present. */
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u32 frag_screen;
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/* All values below the aligned_u64 must be 64 bit. */
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aligned_u64 pds_bgnd0_base;
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u64 pds_bgnd1_base;
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u64 pds_bgnd3_sizeinfo;
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u64 isp_mtile_base;
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#define ROGUE_PBE_WORDS_REQUIRED_FOR_TQS 3
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/* TQ_MAX_RENDER_TARGETS * PBE_STATE_SIZE */
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u64 pbe_wordx_mrty[3U * ROGUE_PBE_WORDS_REQUIRED_FOR_TQS];
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};
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struct rogue_fwif_cmd_transfer {
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/* Common command attributes */
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struct rogue_fwif_cmd_common common __aligned(8);
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struct rogue_fwif_transfer_regs regs __aligned(8);
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u32 flags;
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u32 padding;
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};
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#include "pvr_rogue_fwif_client_check.h"
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#endif /* PVR_ROGUE_FWIF_CLIENT_H */
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