46c5338db7
The cortina/gemini SL3516 SoC has a crypto IP name either (crypto engine/crypto acceleration engine in the datasheet). It support many algorithms like [AES|DES|3DES][ECB|CBC], SHA1, MD5 and some HMAC. This patch adds the core files and support for ecb(aes) and the RNG. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
62 lines
1.2 KiB
C
62 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* sl3516-ce-rng.c - hardware cryptographic offloader for SL3516 SoC.
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*
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* Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
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*
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* This file handle the RNG found in the SL3516 crypto engine
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*/
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#include "sl3516-ce.h"
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#include <linux/pm_runtime.h>
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#include <linux/hw_random.h>
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static int sl3516_ce_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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{
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struct sl3516_ce_dev *ce;
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u32 *data = buf;
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size_t read = 0;
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int err;
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ce = container_of(rng, struct sl3516_ce_dev, trng);
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#ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG
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ce->hwrng_stat_req++;
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ce->hwrng_stat_bytes += max;
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#endif
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err = pm_runtime_get_sync(ce->dev);
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if (err < 0) {
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pm_runtime_put_noidle(ce->dev);
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return err;
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}
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while (read < max) {
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*data = readl(ce->base + IPSEC_RAND_NUM_REG);
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data++;
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read += 4;
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}
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pm_runtime_put(ce->dev);
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return read;
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}
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int sl3516_ce_rng_register(struct sl3516_ce_dev *ce)
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{
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int ret;
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ce->trng.name = "SL3516 Crypto Engine RNG";
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ce->trng.read = sl3516_ce_rng_read;
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ce->trng.quality = 700;
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ret = hwrng_register(&ce->trng);
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if (ret)
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dev_err(ce->dev, "Fail to register the RNG\n");
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return ret;
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}
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void sl3516_ce_rng_unregister(struct sl3516_ce_dev *ce)
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{
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hwrng_unregister(&ce->trng);
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}
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