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linux/drivers/clk/qcom/gpucc-sa8775p.c
Taniya Das 211681998d clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's 
Update wait_val fields as per the default hardware values of the GDSC as
otherwise it would lead to GDSC FSM state stuck causing power on/off
failures of the GSDC.

Fixes: 0afa16afc3 ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-6-adcc756a23df@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23 17:14:05 -05:00

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2020000000, 0 },
};
/* 810MHz configuration */
static struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x2a,
.alpha = 0x3000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00400805,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 1000MHz configuration */
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x34,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00400805,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x9430,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x942c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cb_clk = {
.halt_reg = 0x93a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cb_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x9130,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_demet_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_demet_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_demet_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
};
static struct gdsc cx_gdsc = {
.gdscr = 0x9108,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.gds_hw_ctrl = 0x953c,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x905c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = AON_RESET | RETAIN_FF_ENABLE,
};
static struct gdsc *gpu_cc_sa8775p_gdscs[] = {
[GPU_CC_CX_GDSC] = &cx_gdsc,
[GPU_CC_GX_GDSC] = &gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_CB_BCR] = { 0x93a0 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
};
static const struct regmap_config gpu_cc_sa8775p_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
.config = &gpu_cc_sa8775p_regmap_config,
.clks = gpu_cc_sa8775p_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks),
.resets = gpu_cc_sa8775p_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets),
.gdscs = gpu_cc_sa8775p_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs),
};
static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
{ .compatible = "qcom,sa8775p-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table);
static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sa8775p_desc, regmap);
}
static struct platform_driver gpu_cc_sa8775p_driver = {
.probe = gpu_cc_sa8775p_probe,
.driver = {
.name = "gpu_cc-sa8775p",
.of_match_table = gpu_cc_sa8775p_match_table,
},
};
module_platform_driver(gpu_cc_sa8775p_driver);
MODULE_DESCRIPTION("SA8775P GPUCC driver");
MODULE_LICENSE("GPL");
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