4f07118f65
It appears that a memory barrier soon after a mispredicted branch, not just in the delay slot, can cause the hang condition of this cpu errata. So move them out-of-line, and explicitly put them into a "branch always, predict taken" delay slot which should fully kill this problem. Signed-off-by: David S. Miller <davem@davemloft.net>
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
/* $Id: atomic.h,v 1.22 2001/07/11 23:56:07 davem Exp $
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* atomic.h: Thankfully the V9 is at least reasonable for this
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* stuff.
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*
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* Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)
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*/
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#ifndef __ARCH_SPARC64_ATOMIC__
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#define __ARCH_SPARC64_ATOMIC__
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#include <linux/config.h>
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#include <linux/types.h>
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typedef struct { volatile int counter; } atomic_t;
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typedef struct { volatile __s64 counter; } atomic64_t;
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#define ATOMIC_INIT(i) { (i) }
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic64_read(v) ((v)->counter)
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#define atomic_set(v, i) (((v)->counter) = i)
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#define atomic64_set(v, i) (((v)->counter) = i)
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extern void atomic_add(int, atomic_t *);
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extern void atomic64_add(int, atomic64_t *);
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extern void atomic_sub(int, atomic_t *);
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extern void atomic64_sub(int, atomic64_t *);
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extern int atomic_add_ret(int, atomic_t *);
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extern int atomic64_add_ret(int, atomic64_t *);
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extern int atomic_sub_ret(int, atomic_t *);
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extern int atomic64_sub_ret(int, atomic64_t *);
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#define atomic_dec_return(v) atomic_sub_ret(1, v)
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#define atomic64_dec_return(v) atomic64_sub_ret(1, v)
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#define atomic_inc_return(v) atomic_add_ret(1, v)
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#define atomic64_inc_return(v) atomic64_add_ret(1, v)
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#define atomic_sub_return(i, v) atomic_sub_ret(i, v)
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#define atomic64_sub_return(i, v) atomic64_sub_ret(i, v)
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#define atomic_add_return(i, v) atomic_add_ret(i, v)
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#define atomic64_add_return(i, v) atomic64_add_ret(i, v)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
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#define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)
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#define atomic64_dec_and_test(v) (atomic64_sub_ret(1, v) == 0)
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#define atomic_inc(v) atomic_add(1, v)
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#define atomic64_inc(v) atomic64_add(1, v)
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#define atomic_dec(v) atomic_sub(1, v)
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#define atomic64_dec(v) atomic64_sub(1, v)
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#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
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#define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)
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/* Atomic operations are already serializing */
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#ifdef CONFIG_SMP
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#define smp_mb__before_atomic_dec() membar_storeload_loadload();
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#define smp_mb__after_atomic_dec() membar_storeload_storestore();
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#define smp_mb__before_atomic_inc() membar_storeload_loadload();
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#define smp_mb__after_atomic_inc() membar_storeload_storestore();
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#else
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#endif
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#endif /* !(__ARCH_SPARC64_ATOMIC__) */
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