601 lines
15 KiB
C
601 lines
15 KiB
C
/*
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* Promise TX2/TX4/TX2000/133 IDE driver
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Split from:
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* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
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* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2005-2007 MontaVista Software, Inc.
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* Portions Copyright (C) 1999 Promise Technology, Inc.
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* Author: Frank Tiernan (frankt@promise.com)
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* Released under terms of General Public License
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#ifdef CONFIG_PPC_PMAC
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#endif
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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static const char *pdc_quirk_drives[] = {
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"QUANTUM FIREBALLlct08 08",
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"QUANTUM FIREBALLP KA6.4",
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"QUANTUM FIREBALLP KA9.1",
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"QUANTUM FIREBALLP LM20.4",
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"QUANTUM FIREBALLP KX13.6",
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"QUANTUM FIREBALLP KX20.5",
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"QUANTUM FIREBALLP KX27.3",
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"QUANTUM FIREBALLP LM20.5",
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NULL
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};
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static u8 max_dma_rate(struct pci_dev *pdev)
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{
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u8 mode;
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switch(pdev->device) {
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case PCI_DEVICE_ID_PROMISE_20277:
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case PCI_DEVICE_ID_PROMISE_20276:
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case PCI_DEVICE_ID_PROMISE_20275:
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case PCI_DEVICE_ID_PROMISE_20271:
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case PCI_DEVICE_ID_PROMISE_20269:
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mode = 4;
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break;
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case PCI_DEVICE_ID_PROMISE_20270:
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case PCI_DEVICE_ID_PROMISE_20268:
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mode = 3;
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break;
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default:
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return 0;
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}
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return mode;
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}
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/**
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* get_indexed_reg - Get indexed register
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* @hwif: for the port address
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* @index: index of the indexed register
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*/
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static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
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{
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u8 value;
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outb(index, hwif->dma_vendor1);
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value = inb(hwif->dma_vendor3);
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DBG("index[%02X] value[%02X]\n", index, value);
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return value;
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}
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/**
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* set_indexed_reg - Set indexed register
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* @hwif: for the port address
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* @index: index of the indexed register
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*/
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static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
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{
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outb(index, hwif->dma_vendor1);
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outb(value, hwif->dma_vendor3);
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DBG("index[%02X] value[%02X]\n", index, value);
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}
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/*
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* ATA Timing Tables based on 133 MHz PLL output clock.
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*
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* If the PLL outputs 100 MHz clock, the ASIC hardware will set
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* the timing registers automatically when "set features" command is
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* issued to the device. However, if the PLL output clock is 133 MHz,
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* the following tables must be used.
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*/
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static struct pio_timing {
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u8 reg0c, reg0d, reg13;
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} pio_timings [] = {
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{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
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{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
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{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
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{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
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{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
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};
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static struct mwdma_timing {
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u8 reg0e, reg0f;
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} mwdma_timings [] = {
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{ 0xdf, 0x5f }, /* MWDMA mode 0 */
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{ 0x6b, 0x27 }, /* MWDMA mode 1 */
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{ 0x69, 0x25 }, /* MWDMA mode 2 */
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};
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static struct udma_timing {
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u8 reg10, reg11, reg12;
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} udma_timings [] = {
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{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
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{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
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{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
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{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
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{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
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{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
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{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
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};
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static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
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/*
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* IDE core issues SETFEATURES_XFER to the drive first (thanks to
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* IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
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* automatically set the timing registers based on 100 MHz PLL output.
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*
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* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
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* chips, we must override the default register settings...
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*/
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if (max_dma_rate(hwif->pci_dev) == 4) {
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u8 mode = speed & 0x07;
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switch (speed) {
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case XFER_UDMA_6:
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case XFER_UDMA_5:
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case XFER_UDMA_4:
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case XFER_UDMA_3:
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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set_indexed_reg(hwif, 0x10 + adj,
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udma_timings[mode].reg10);
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set_indexed_reg(hwif, 0x11 + adj,
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udma_timings[mode].reg11);
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set_indexed_reg(hwif, 0x12 + adj,
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udma_timings[mode].reg12);
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break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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set_indexed_reg(hwif, 0x0e + adj,
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mwdma_timings[mode].reg0e);
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set_indexed_reg(hwif, 0x0f + adj,
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mwdma_timings[mode].reg0f);
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break;
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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set_indexed_reg(hwif, 0x0c + adj,
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pio_timings[mode].reg0c);
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set_indexed_reg(hwif, 0x0d + adj,
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pio_timings[mode].reg0d);
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set_indexed_reg(hwif, 0x13 + adj,
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pio_timings[mode].reg13);
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break;
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default:
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printk(KERN_ERR "pdc202xx_new: "
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"Unknown speed %d ignored\n", speed);
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}
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} else if (speed == XFER_UDMA_2) {
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/* Set tHOLD bit to 0 if using UDMA mode 2 */
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u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
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set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
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}
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}
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static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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pdcnew_set_mode(drive, XFER_PIO_0 + pio);
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}
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static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
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{
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if (get_indexed_reg(hwif, 0x0b) & 0x04)
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return ATA_CBL_PATA40;
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else
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return ATA_CBL_PATA80;
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}
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static int pdcnew_quirkproc(ide_drive_t *drive)
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{
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const char **list, *model = drive->id->model;
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for (list = pdc_quirk_drives; *list != NULL; list++)
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if (strstr(model, *list) != NULL)
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return 2;
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return 0;
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}
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static void pdcnew_reset(ide_drive_t *drive)
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{
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/*
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* Deleted this because it is redundant from the caller.
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*/
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printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
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HWIF(drive)->channel ? "Secondary" : "Primary");
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}
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/**
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* read_counter - Read the byte count registers
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* @dma_base: for the port address
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*/
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static long __devinit read_counter(u32 dma_base)
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{
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u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
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u8 cnt0, cnt1, cnt2, cnt3;
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long count = 0, last;
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int retry = 3;
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do {
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last = count;
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/* Read the current count */
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outb(0x20, pri_dma_base + 0x01);
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cnt0 = inb(pri_dma_base + 0x03);
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outb(0x21, pri_dma_base + 0x01);
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cnt1 = inb(pri_dma_base + 0x03);
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outb(0x20, sec_dma_base + 0x01);
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cnt2 = inb(sec_dma_base + 0x03);
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outb(0x21, sec_dma_base + 0x01);
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cnt3 = inb(sec_dma_base + 0x03);
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count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
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/*
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* The 30-bit decrementing counter is read in 4 pieces.
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* Incorrect value may be read when the most significant bytes
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* are changing...
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*/
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} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
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DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
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cnt0, cnt1, cnt2, cnt3);
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return count;
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}
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/**
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* detect_pll_input_clock - Detect the PLL input clock in Hz.
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* @dma_base: for the port address
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* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
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*/
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static long __devinit detect_pll_input_clock(unsigned long dma_base)
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{
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struct timeval start_time, end_time;
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long start_count, end_count;
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long pll_input, usec_elapsed;
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u8 scr1;
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start_count = read_counter(dma_base);
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do_gettimeofday(&start_time);
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/* Start the test mode */
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outb(0x01, dma_base + 0x01);
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scr1 = inb(dma_base + 0x03);
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DBG("scr1[%02X]\n", scr1);
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outb(scr1 | 0x40, dma_base + 0x03);
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/* Let the counter run for 10 ms. */
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mdelay(10);
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end_count = read_counter(dma_base);
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do_gettimeofday(&end_time);
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/* Stop the test mode */
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outb(0x01, dma_base + 0x01);
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scr1 = inb(dma_base + 0x03);
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DBG("scr1[%02X]\n", scr1);
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outb(scr1 & ~0x40, dma_base + 0x03);
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/*
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* Calculate the input clock in Hz
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* (the clock counter is 30 bit wide and counts down)
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*/
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usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
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(end_time.tv_usec - start_time.tv_usec);
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pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
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(10000000 / usec_elapsed);
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DBG("start[%ld] end[%ld]\n", start_count, end_count);
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return pll_input;
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}
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#ifdef CONFIG_PPC_PMAC
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static void __devinit apple_kiwi_init(struct pci_dev *pdev)
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{
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struct device_node *np = pci_device_to_OF_node(pdev);
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u8 conf;
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if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
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return;
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if (pdev->revision >= 0x03) {
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/* Setup chip magic config stuff (from darwin) */
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pci_read_config_byte (pdev, 0x40, &conf);
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pci_write_config_byte(pdev, 0x40, (conf | 0x01));
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}
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}
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#endif /* CONFIG_PPC_PMAC */
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static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
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{
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unsigned long dma_base = pci_resource_start(dev, 4);
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unsigned long sec_dma_base = dma_base + 0x08;
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long pll_input, pll_output, ratio;
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int f, r;
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u8 pll_ctl0, pll_ctl1;
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if (dma_base == 0)
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return -EFAULT;
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#ifdef CONFIG_PPC_PMAC
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apple_kiwi_init(dev);
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#endif
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/* Calculate the required PLL output frequency */
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switch(max_dma_rate(dev)) {
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case 4: /* it's 133 MHz for Ultra133 chips */
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pll_output = 133333333;
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break;
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case 3: /* and 100 MHz for Ultra100 chips */
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default:
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pll_output = 100000000;
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break;
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}
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/*
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* Detect PLL input clock.
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* On some systems, where PCI bus is running at non-standard clock rate
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* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
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* PDC20268 and newer chips employ PLL circuit to help correct timing
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* registers setting.
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*/
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pll_input = detect_pll_input_clock(dma_base);
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printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
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/* Sanity check */
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if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
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printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
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name, pll_input);
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goto out;
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}
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#ifdef DEBUG
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DBG("pll_output is %ld Hz\n", pll_output);
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/* Show the current clock value of PLL control register
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* (maybe already configured by the BIOS)
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*/
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outb(0x02, sec_dma_base + 0x01);
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pll_ctl0 = inb(sec_dma_base + 0x03);
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outb(0x03, sec_dma_base + 0x01);
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pll_ctl1 = inb(sec_dma_base + 0x03);
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DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
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#endif
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/*
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* Calculate the ratio of F, R and NO
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* POUT = (F + 2) / (( R + 2) * NO)
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*/
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ratio = pll_output / (pll_input / 1000);
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if (ratio < 8600L) { /* 8.6x */
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/* Using NO = 0x01, R = 0x0d */
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r = 0x0d;
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} else if (ratio < 12900L) { /* 12.9x */
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/* Using NO = 0x01, R = 0x08 */
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r = 0x08;
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} else if (ratio < 16100L) { /* 16.1x */
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/* Using NO = 0x01, R = 0x06 */
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r = 0x06;
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} else if (ratio < 64000L) { /* 64x */
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r = 0x00;
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} else {
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/* Invalid ratio */
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printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
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goto out;
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}
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f = (ratio * (r + 2)) / 1000 - 2;
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DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
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if (unlikely(f < 0 || f > 127)) {
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/* Invalid F */
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printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
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goto out;
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}
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pll_ctl0 = (u8) f;
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pll_ctl1 = (u8) r;
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DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
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outb(0x02, sec_dma_base + 0x01);
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outb(pll_ctl0, sec_dma_base + 0x03);
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outb(0x03, sec_dma_base + 0x01);
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outb(pll_ctl1, sec_dma_base + 0x03);
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/* Wait the PLL circuit to be stable */
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mdelay(30);
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#ifdef DEBUG
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/*
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* Show the current clock value of PLL control register
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*/
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outb(0x02, sec_dma_base + 0x01);
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pll_ctl0 = inb(sec_dma_base + 0x03);
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outb(0x03, sec_dma_base + 0x01);
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pll_ctl1 = inb(sec_dma_base + 0x03);
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DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
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#endif
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out:
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return dev->irq;
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}
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static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
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{
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hwif->set_pio_mode = &pdcnew_set_pio_mode;
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hwif->set_dma_mode = &pdcnew_set_mode;
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hwif->quirkproc = &pdcnew_quirkproc;
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hwif->resetproc = &pdcnew_reset;
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if (hwif->dma_base == 0)
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return;
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if (hwif->cbl != ATA_CBL_PATA40_SHORT)
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hwif->cbl = pdcnew_cable_detect(hwif);
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}
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static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
|
|
{
|
|
struct pci_dev *dev2;
|
|
|
|
dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
|
|
PCI_FUNC(dev->devfn)));
|
|
if (dev2 &&
|
|
dev2->vendor == dev->vendor &&
|
|
dev2->device == dev->device) {
|
|
|
|
if (dev2->irq != dev->irq) {
|
|
dev2->irq = dev->irq;
|
|
printk(KERN_INFO "PDC20270: PCI config space "
|
|
"interrupt fixed\n");
|
|
}
|
|
|
|
return dev2;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
#define DECLARE_PDCNEW_DEV(name_str, udma) \
|
|
{ \
|
|
.name = name_str, \
|
|
.init_chipset = init_chipset_pdcnew, \
|
|
.init_hwif = init_hwif_pdc202new, \
|
|
.host_flags = IDE_HFLAG_POST_SET_MODE | \
|
|
IDE_HFLAG_ERROR_STOPS_FIFO | \
|
|
IDE_HFLAG_OFF_BOARD, \
|
|
.pio_mask = ATA_PIO4, \
|
|
.mwdma_mask = ATA_MWDMA2, \
|
|
.udma_mask = udma, \
|
|
}
|
|
|
|
static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
|
|
/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
|
|
/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
|
|
/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
|
|
/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
|
|
/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
|
|
/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
|
|
/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
|
|
};
|
|
|
|
/**
|
|
* pdc202new_init_one - called when a pdc202xx is found
|
|
* @dev: the pdc202new device
|
|
* @id: the matching pci id
|
|
*
|
|
* Called when the PCI registration layer (or the IDE initialization)
|
|
* finds a device matching our IDE device tables.
|
|
*/
|
|
|
|
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
const struct ide_port_info *d;
|
|
struct pci_dev *bridge = dev->bus->self;
|
|
u8 idx = id->driver_data;
|
|
|
|
d = &pdcnew_chipsets[idx];
|
|
|
|
if (idx == 2 && bridge &&
|
|
bridge->vendor == PCI_VENDOR_ID_DEC &&
|
|
bridge->device == PCI_DEVICE_ID_DEC_21150) {
|
|
struct pci_dev *dev2;
|
|
|
|
if (PCI_SLOT(dev->devfn) & 2)
|
|
return -ENODEV;
|
|
|
|
dev2 = pdc20270_get_dev2(dev);
|
|
|
|
if (dev2) {
|
|
int ret = ide_setup_pci_devices(dev, dev2, d);
|
|
if (ret < 0)
|
|
pci_dev_put(dev2);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (idx == 5 && bridge &&
|
|
bridge->vendor == PCI_VENDOR_ID_INTEL &&
|
|
(bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
|
|
bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
|
|
printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
|
|
"skipping\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return ide_setup_pci_device(dev, d);
|
|
}
|
|
|
|
static const struct pci_device_id pdc202new_pci_tbl[] = {
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "Promise_IDE",
|
|
.id_table = pdc202new_pci_tbl,
|
|
.probe = pdc202new_init_one,
|
|
};
|
|
|
|
static int __init pdc202new_ide_init(void)
|
|
{
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
module_init(pdc202new_ide_init);
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
|
|
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
|
|
MODULE_LICENSE("GPL");
|