87246b7567
For a given SDRAM clock rate, SDRAM chips require memory controllers to use a specific set of timing minimums and maximums to transfer data reliably. These parameters can be different for different memory chips and can also potentially vary by board. This patch adds the infrastructure for board-*.c files to pass this timing data to the SDRAM controller init function. The timing data is specified in an 'omap_sdrc_params' structure, in terms of SDRC controller register values. An array of these structs, one per SDRC target clock rate, is passed by the board-*.c file to omap2_init_common_hw(). This patch does not define the values for different memory chips, nor does it use the values for anything; those will come in subsequent patches. linux-omap source commit is bc84ecfc795c2d1c5cda8da4127cf972f488a696. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* SMS/SDRC (SDRAM controller) common code for OMAP2/3
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*
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* Copyright (C) 2005, 2008 Texas Instruments Inc.
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* Copyright (C) 2005, 2008 Nokia Corporation
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*
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* Tony Lindgren <tony@atomide.com>
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* Paul Walmsley
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <mach/clock.h>
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#include <mach/sram.h>
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#include "prm.h"
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#include <mach/sdrc.h>
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#include "sdrc.h"
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static struct omap_sdrc_params *sdrc_init_params;
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void __iomem *omap2_sdrc_base;
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void __iomem *omap2_sms_base;
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/**
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* omap2_sdrc_get_params - return SDRC register values for a given clock rate
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* @r: SDRC clock rate (in Hz)
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*
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* Return pre-calculated values for the SDRC_ACTIM_CTRLA,
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* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
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* SDRC clock rate 'r'. These parameters control various timing
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* delays in the SDRAM controller that are expressed in terms of the
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* number of SDRC clock cycles to wait; hence the clock rate
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* dependency. Note that sdrc_init_params must be sorted rate
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* descending. Also assumes that both chip-selects use the same
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* timing parameters. Returns a struct omap_sdrc_params * upon
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* success, or NULL upon failure.
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*/
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struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
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{
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struct omap_sdrc_params *sp;
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sp = sdrc_init_params;
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while (sp->rate != r)
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sp++;
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if (!sp->rate)
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return NULL;
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return sp;
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}
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void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
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{
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omap2_sdrc_base = omap2_globals->sdrc;
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omap2_sms_base = omap2_globals->sms;
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}
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/* turn on smart idle modes for SDRAM scheduler and controller */
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void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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{
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u32 l;
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l = sms_read_reg(SMS_SYSCONFIG);
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l &= ~(0x3 << 3);
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l |= (0x2 << 3);
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sms_write_reg(l, SMS_SYSCONFIG);
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l = sdrc_read_reg(SDRC_SYSCONFIG);
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l &= ~(0x3 << 3);
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l |= (0x2 << 3);
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sdrc_write_reg(l, SDRC_SYSCONFIG);
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sdrc_init_params = sp;
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}
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