868ea0c925
On Tue, Jun 20, 2006 at 02:01:26PM +1000, Benjamin Herrenschmidt wrote: > On Mon, 2006-06-19 at 13:08 -0700, Mark A. Greer wrote: > > MPC10x-style interrupt controllers have a serial mode that allows > > several interrupts to be clocked in through one INT signal. > > > > This patch adds the software support for that mode. > > You hard code the clock ratio... why not add a separate call to be > called after mpic_init, > something like mpic_set_serial_int(int mpic, int enable, int > clock_ratio) ? How's this? -- MPC10x-style interrupt controllers have a serial mode that allows several interrupts to be clocked in through one INT signal. This patch adds the software support for that mode. Signed-off-by: Mark A. Greer <mgreer@mvista.com> -- arch/powerpc/sysdev/mpic.c | 20 ++++++++++++++++++++ include/asm-powerpc/mpic.h | 10 ++++++++++ 2 files changed, 30 insertions(+) -- Signed-off-by: Paul Mackerras <paulus@samba.org>
1065 lines
28 KiB
C
1065 lines
28 KiB
C
/*
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* arch/powerpc/kernel/mpic.c
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*
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* Driver for interrupt controllers following the OpenPIC standard, the
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* common implementation beeing IBM's MPIC. This driver also can deal
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* with various broken implementations of this HW.
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*
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* Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#undef DEBUG
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#undef DEBUG_IPI
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#undef DEBUG_IRQ
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#undef DEBUG_LOW
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/bootmem.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <asm/ptrace.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/machdep.h>
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#include <asm/mpic.h>
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#include <asm/smp.h>
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#ifdef DEBUG
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static struct mpic *mpics;
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static struct mpic *mpic_primary;
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static DEFINE_SPINLOCK(mpic_lock);
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#ifdef CONFIG_PPC32 /* XXX for now */
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#ifdef CONFIG_IRQ_ALL_CPUS
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#define distribute_irqs (1)
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#else
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#define distribute_irqs (0)
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#endif
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#endif
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/*
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* Register accessor functions
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*/
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static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
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unsigned int reg)
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{
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if (be)
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return in_be32(base + (reg >> 2));
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else
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return in_le32(base + (reg >> 2));
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}
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static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
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unsigned int reg, u32 value)
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{
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if (be)
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out_be32(base + (reg >> 2), value);
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else
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out_le32(base + (reg >> 2), value);
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}
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static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
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{
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unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
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unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
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if (mpic->flags & MPIC_BROKEN_IPI)
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be = !be;
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return _mpic_read(be, mpic->gregs, offset);
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}
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static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
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{
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unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
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_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
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}
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static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
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{
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unsigned int cpu = 0;
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg);
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}
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static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
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{
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unsigned int cpu = 0;
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
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}
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static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
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{
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unsigned int isu = src_no >> mpic->isu_shift;
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unsigned int idx = src_no & mpic->isu_mask;
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return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
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reg + (idx * MPIC_IRQ_STRIDE));
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}
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static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
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unsigned int reg, u32 value)
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{
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unsigned int isu = src_no >> mpic->isu_shift;
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unsigned int idx = src_no & mpic->isu_mask;
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_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
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reg + (idx * MPIC_IRQ_STRIDE), value);
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}
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#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
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#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
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#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
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#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
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#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
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#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
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#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
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#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
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/*
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* Low level utility functions
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*/
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/* Check if we have one of those nice broken MPICs with a flipped endian on
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* reads from IPI registers
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*/
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static void __init mpic_test_broken_ipi(struct mpic *mpic)
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{
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u32 r;
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mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
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r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
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if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
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printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
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mpic->flags |= MPIC_BROKEN_IPI;
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}
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}
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#ifdef CONFIG_MPIC_BROKEN_U3
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/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
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* to force the edge setting on the MPIC and do the ack workaround.
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*/
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
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{
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if (source >= 128 || !mpic->fixups)
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return 0;
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return mpic->fixups[source].base != NULL;
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}
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static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
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{
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struct mpic_irq_fixup *fixup = &mpic->fixups[source];
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if (fixup->applebase) {
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unsigned int soff = (fixup->index >> 3) & ~3;
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unsigned int mask = 1U << (fixup->index & 0x1f);
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writel(mask, fixup->applebase + soff);
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} else {
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spin_lock(&mpic->fixup_lock);
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writeb(0x11 + 2 * fixup->index, fixup->base + 2);
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writel(fixup->data, fixup->base + 4);
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spin_unlock(&mpic->fixup_lock);
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}
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}
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static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
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unsigned int irqflags)
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{
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struct mpic_irq_fixup *fixup = &mpic->fixups[source];
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unsigned long flags;
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u32 tmp;
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if (fixup->base == NULL)
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return;
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DBG("startup_ht_interrupt(%u, %u) index: %d\n",
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source, irqflags, fixup->index);
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spin_lock_irqsave(&mpic->fixup_lock, flags);
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/* Enable and configure */
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writeb(0x10 + 2 * fixup->index, fixup->base + 2);
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tmp = readl(fixup->base + 4);
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tmp &= ~(0x23U);
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if (irqflags & IRQ_LEVEL)
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tmp |= 0x22;
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writel(tmp, fixup->base + 4);
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spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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}
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static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
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unsigned int irqflags)
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{
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struct mpic_irq_fixup *fixup = &mpic->fixups[source];
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unsigned long flags;
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u32 tmp;
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if (fixup->base == NULL)
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return;
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DBG("shutdown_ht_interrupt(%u, %u)\n", source, irqflags);
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/* Disable */
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spin_lock_irqsave(&mpic->fixup_lock, flags);
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writeb(0x10 + 2 * fixup->index, fixup->base + 2);
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tmp = readl(fixup->base + 4);
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tmp |= 1;
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writel(tmp, fixup->base + 4);
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spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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}
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static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
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unsigned int devfn, u32 vdid)
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{
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int i, irq, n;
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u8 __iomem *base;
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u32 tmp;
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u8 pos;
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for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
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pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
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u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
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if (id == PCI_CAP_ID_HT_IRQCONF) {
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id = readb(devbase + pos + 3);
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if (id == 0x80)
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break;
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}
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}
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if (pos == 0)
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return;
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base = devbase + pos;
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writeb(0x01, base + 2);
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n = (readl(base + 4) >> 16) & 0xff;
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printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
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" has %d irqs\n",
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devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
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for (i = 0; i <= n; i++) {
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writeb(0x10 + 2 * i, base + 2);
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tmp = readl(base + 4);
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irq = (tmp >> 16) & 0xff;
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DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
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/* mask it , will be unmasked later */
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tmp |= 0x1;
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writel(tmp, base + 4);
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mpic->fixups[irq].index = i;
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mpic->fixups[irq].base = base;
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/* Apple HT PIC has a non-standard way of doing EOIs */
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if ((vdid & 0xffff) == 0x106b)
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mpic->fixups[irq].applebase = devbase + 0x60;
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else
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mpic->fixups[irq].applebase = NULL;
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writeb(0x11 + 2 * i, base + 2);
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mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
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}
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}
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static void __init mpic_scan_ht_pics(struct mpic *mpic)
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{
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unsigned int devfn;
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u8 __iomem *cfgspace;
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printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
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/* Allocate fixups array */
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mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
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BUG_ON(mpic->fixups == NULL);
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memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
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/* Init spinlock */
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spin_lock_init(&mpic->fixup_lock);
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/* Map U3 config space. We assume all IO-APICs are on the primary bus
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* so we only need to map 64kB.
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*/
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cfgspace = ioremap(0xf2000000, 0x10000);
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BUG_ON(cfgspace == NULL);
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/* Now we scan all slots. We do a very quick scan, we read the header
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* type, vendor ID and device ID only, that's plenty enough
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*/
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for (devfn = 0; devfn < 0x100; devfn++) {
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u8 __iomem *devbase = cfgspace + (devfn << 8);
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u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
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u32 l = readl(devbase + PCI_VENDOR_ID);
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u16 s;
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DBG("devfn %x, l: %x\n", devfn, l);
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/* If no device, skip */
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if (l == 0xffffffff || l == 0x00000000 ||
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l == 0x0000ffff || l == 0xffff0000)
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goto next;
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/* Check if is supports capability lists */
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s = readw(devbase + PCI_STATUS);
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if (!(s & PCI_STATUS_CAP_LIST))
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goto next;
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mpic_scan_ht_pic(mpic, devbase, devfn, l);
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next:
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/* next device, if function 0 */
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if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
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devfn += 7;
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}
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}
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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/* Find an mpic associated with a given linux interrupt */
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static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
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{
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struct mpic *mpic = mpics;
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while(mpic) {
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/* search IPIs first since they may override the main interrupts */
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if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
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if (is_ipi)
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*is_ipi = 1;
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return mpic;
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}
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if (irq >= mpic->irq_offset &&
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irq < (mpic->irq_offset + mpic->irq_count)) {
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if (is_ipi)
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*is_ipi = 0;
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return mpic;
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}
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mpic = mpic -> next;
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}
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return NULL;
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}
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/* Convert a cpu mask from logical to physical cpu numbers. */
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static inline u32 mpic_physmask(u32 cpumask)
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{
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int i;
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u32 mask = 0;
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for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
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mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
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return mask;
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}
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#ifdef CONFIG_SMP
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/* Get the mpic structure from the IPI number */
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static inline struct mpic * mpic_from_ipi(unsigned int ipi)
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{
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return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
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}
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#endif
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/* Get the mpic structure from the irq number */
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static inline struct mpic * mpic_from_irq(unsigned int irq)
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{
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return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
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}
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/* Send an EOI */
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static inline void mpic_eoi(struct mpic *mpic)
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{
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mpic_cpu_write(MPIC_CPU_EOI, 0);
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(void)mpic_cpu_read(MPIC_CPU_WHOAMI);
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}
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#ifdef CONFIG_SMP
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static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct mpic *mpic = dev_id;
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smp_message_recv(irq - mpic->ipi_offset, regs);
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return IRQ_HANDLED;
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}
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#endif /* CONFIG_SMP */
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/*
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* Linux descriptor level callbacks
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*/
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static void mpic_enable_irq(unsigned int irq)
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{
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unsigned int loops = 100000;
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struct mpic *mpic = mpic_from_irq(irq);
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unsigned int src = irq - mpic->irq_offset;
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DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
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mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
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mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
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~MPIC_VECPRI_MASK);
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/* make sure mask gets to controller before we return to user */
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do {
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if (!loops--) {
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printk(KERN_ERR "mpic_enable_irq timeout\n");
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break;
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}
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} while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
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#ifdef CONFIG_MPIC_BROKEN_U3
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if (mpic->flags & MPIC_BROKEN_U3) {
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unsigned int src = irq - mpic->irq_offset;
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if (mpic_is_ht_interrupt(mpic, src) &&
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(irq_desc[irq].status & IRQ_LEVEL))
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mpic_ht_end_irq(mpic, src);
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}
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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}
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static unsigned int mpic_startup_irq(unsigned int irq)
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{
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#ifdef CONFIG_MPIC_BROKEN_U3
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struct mpic *mpic = mpic_from_irq(irq);
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unsigned int src = irq - mpic->irq_offset;
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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mpic_enable_irq(irq);
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#ifdef CONFIG_MPIC_BROKEN_U3
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if (mpic_is_ht_interrupt(mpic, src))
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mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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return 0;
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}
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static void mpic_disable_irq(unsigned int irq)
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{
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unsigned int loops = 100000;
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struct mpic *mpic = mpic_from_irq(irq);
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unsigned int src = irq - mpic->irq_offset;
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DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
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|
|
mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
|
|
mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
|
|
MPIC_VECPRI_MASK);
|
|
|
|
/* make sure mask gets to controller before we return to user */
|
|
do {
|
|
if (!loops--) {
|
|
printk(KERN_ERR "mpic_enable_irq timeout\n");
|
|
break;
|
|
}
|
|
} while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
|
|
}
|
|
|
|
static void mpic_shutdown_irq(unsigned int irq)
|
|
{
|
|
#ifdef CONFIG_MPIC_BROKEN_U3
|
|
struct mpic *mpic = mpic_from_irq(irq);
|
|
unsigned int src = irq - mpic->irq_offset;
|
|
|
|
if (mpic_is_ht_interrupt(mpic, src))
|
|
mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
|
|
|
|
#endif /* CONFIG_MPIC_BROKEN_U3 */
|
|
|
|
mpic_disable_irq(irq);
|
|
}
|
|
|
|
static void mpic_end_irq(unsigned int irq)
|
|
{
|
|
struct mpic *mpic = mpic_from_irq(irq);
|
|
|
|
#ifdef DEBUG_IRQ
|
|
DBG("%s: end_irq: %d\n", mpic->name, irq);
|
|
#endif
|
|
/* We always EOI on end_irq() even for edge interrupts since that
|
|
* should only lower the priority, the MPIC should have properly
|
|
* latched another edge interrupt coming in anyway
|
|
*/
|
|
|
|
#ifdef CONFIG_MPIC_BROKEN_U3
|
|
if (mpic->flags & MPIC_BROKEN_U3) {
|
|
unsigned int src = irq - mpic->irq_offset;
|
|
if (mpic_is_ht_interrupt(mpic, src) &&
|
|
(irq_desc[irq].status & IRQ_LEVEL))
|
|
mpic_ht_end_irq(mpic, src);
|
|
}
|
|
#endif /* CONFIG_MPIC_BROKEN_U3 */
|
|
|
|
mpic_eoi(mpic);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static void mpic_enable_ipi(unsigned int irq)
|
|
{
|
|
struct mpic *mpic = mpic_from_ipi(irq);
|
|
unsigned int src = irq - mpic->ipi_offset;
|
|
|
|
DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
|
|
mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
|
|
}
|
|
|
|
static void mpic_disable_ipi(unsigned int irq)
|
|
{
|
|
/* NEVER disable an IPI... that's just plain wrong! */
|
|
}
|
|
|
|
static void mpic_end_ipi(unsigned int irq)
|
|
{
|
|
struct mpic *mpic = mpic_from_ipi(irq);
|
|
|
|
/*
|
|
* IPIs are marked IRQ_PER_CPU. This has the side effect of
|
|
* preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
|
|
* applying to them. We EOI them late to avoid re-entering.
|
|
* We mark IPI's with SA_INTERRUPT as they must run with
|
|
* irqs disabled.
|
|
*/
|
|
mpic_eoi(mpic);
|
|
}
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
|
|
{
|
|
struct mpic *mpic = mpic_from_irq(irq);
|
|
|
|
cpumask_t tmp;
|
|
|
|
cpus_and(tmp, cpumask, cpu_online_map);
|
|
|
|
mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
|
|
mpic_physmask(cpus_addr(tmp)[0]));
|
|
}
|
|
|
|
|
|
/*
|
|
* Exported functions
|
|
*/
|
|
|
|
|
|
struct mpic * __init mpic_alloc(unsigned long phys_addr,
|
|
unsigned int flags,
|
|
unsigned int isu_size,
|
|
unsigned int irq_offset,
|
|
unsigned int irq_count,
|
|
unsigned int ipi_offset,
|
|
unsigned char *senses,
|
|
unsigned int senses_count,
|
|
const char *name)
|
|
{
|
|
struct mpic *mpic;
|
|
u32 reg;
|
|
const char *vers;
|
|
int i;
|
|
|
|
mpic = alloc_bootmem(sizeof(struct mpic));
|
|
if (mpic == NULL)
|
|
return NULL;
|
|
|
|
|
|
memset(mpic, 0, sizeof(struct mpic));
|
|
mpic->name = name;
|
|
|
|
mpic->hc_irq.typename = name;
|
|
mpic->hc_irq.startup = mpic_startup_irq;
|
|
mpic->hc_irq.shutdown = mpic_shutdown_irq;
|
|
mpic->hc_irq.enable = mpic_enable_irq;
|
|
mpic->hc_irq.disable = mpic_disable_irq;
|
|
mpic->hc_irq.end = mpic_end_irq;
|
|
if (flags & MPIC_PRIMARY)
|
|
mpic->hc_irq.set_affinity = mpic_set_affinity;
|
|
#ifdef CONFIG_SMP
|
|
mpic->hc_ipi.typename = name;
|
|
mpic->hc_ipi.enable = mpic_enable_ipi;
|
|
mpic->hc_ipi.disable = mpic_disable_ipi;
|
|
mpic->hc_ipi.end = mpic_end_ipi;
|
|
#endif /* CONFIG_SMP */
|
|
|
|
mpic->flags = flags;
|
|
mpic->isu_size = isu_size;
|
|
mpic->irq_offset = irq_offset;
|
|
mpic->irq_count = irq_count;
|
|
mpic->ipi_offset = ipi_offset;
|
|
mpic->num_sources = 0; /* so far */
|
|
mpic->senses = senses;
|
|
mpic->senses_count = senses_count;
|
|
|
|
/* Map the global registers */
|
|
mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
|
|
mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
|
|
BUG_ON(mpic->gregs == NULL);
|
|
|
|
/* Reset */
|
|
if (flags & MPIC_WANTS_RESET) {
|
|
mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
|
|
mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
|
|
| MPIC_GREG_GCONF_RESET);
|
|
while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
|
|
& MPIC_GREG_GCONF_RESET)
|
|
mb();
|
|
}
|
|
|
|
/* Read feature register, calculate num CPUs and, for non-ISU
|
|
* MPICs, num sources as well. On ISU MPICs, sources are counted
|
|
* as ISUs are added
|
|
*/
|
|
reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
|
|
mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
|
|
>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
|
|
if (isu_size == 0)
|
|
mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
|
|
>> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
|
|
|
|
/* Map the per-CPU registers */
|
|
for (i = 0; i < mpic->num_cpus; i++) {
|
|
mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
|
|
i * MPIC_CPU_STRIDE, 0x1000);
|
|
BUG_ON(mpic->cpuregs[i] == NULL);
|
|
}
|
|
|
|
/* Initialize main ISU if none provided */
|
|
if (mpic->isu_size == 0) {
|
|
mpic->isu_size = mpic->num_sources;
|
|
mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
|
|
MPIC_IRQ_STRIDE * mpic->isu_size);
|
|
BUG_ON(mpic->isus[0] == NULL);
|
|
}
|
|
mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
|
|
mpic->isu_mask = (1 << mpic->isu_shift) - 1;
|
|
|
|
/* Display version */
|
|
switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
|
|
case 1:
|
|
vers = "1.0";
|
|
break;
|
|
case 2:
|
|
vers = "1.2";
|
|
break;
|
|
case 3:
|
|
vers = "1.3";
|
|
break;
|
|
default:
|
|
vers = "<unknown>";
|
|
break;
|
|
}
|
|
printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
|
|
name, vers, phys_addr, mpic->num_cpus);
|
|
printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
|
|
mpic->isu_shift, mpic->isu_mask);
|
|
|
|
mpic->next = mpics;
|
|
mpics = mpic;
|
|
|
|
if (flags & MPIC_PRIMARY)
|
|
mpic_primary = mpic;
|
|
|
|
return mpic;
|
|
}
|
|
|
|
void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
|
|
unsigned long phys_addr)
|
|
{
|
|
unsigned int isu_first = isu_num * mpic->isu_size;
|
|
|
|
BUG_ON(isu_num >= MPIC_MAX_ISU);
|
|
|
|
mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
|
|
if ((isu_first + mpic->isu_size) > mpic->num_sources)
|
|
mpic->num_sources = isu_first + mpic->isu_size;
|
|
}
|
|
|
|
void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler,
|
|
void *data)
|
|
{
|
|
struct mpic *mpic = mpic_find(irq, NULL);
|
|
unsigned long flags;
|
|
|
|
/* Synchronization here is a bit dodgy, so don't try to replace cascade
|
|
* interrupts on the fly too often ... but normally it's set up at boot.
|
|
*/
|
|
spin_lock_irqsave(&mpic_lock, flags);
|
|
if (mpic->cascade)
|
|
mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset);
|
|
mpic->cascade = NULL;
|
|
wmb();
|
|
mpic->cascade_vec = irq - mpic->irq_offset;
|
|
mpic->cascade_data = data;
|
|
wmb();
|
|
mpic->cascade = handler;
|
|
mpic_enable_irq(irq);
|
|
spin_unlock_irqrestore(&mpic_lock, flags);
|
|
}
|
|
|
|
void __init mpic_init(struct mpic *mpic)
|
|
{
|
|
int i;
|
|
|
|
BUG_ON(mpic->num_sources == 0);
|
|
|
|
printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
|
|
|
|
/* Set current processor priority to max */
|
|
mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
|
|
|
|
/* Initialize timers: just disable them all */
|
|
for (i = 0; i < 4; i++) {
|
|
mpic_write(mpic->tmregs,
|
|
i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
|
|
mpic_write(mpic->tmregs,
|
|
i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
|
|
MPIC_VECPRI_MASK |
|
|
(MPIC_VEC_TIMER_0 + i));
|
|
}
|
|
|
|
/* Initialize IPIs to our reserved vectors and mark them disabled for now */
|
|
mpic_test_broken_ipi(mpic);
|
|
for (i = 0; i < 4; i++) {
|
|
mpic_ipi_write(i,
|
|
MPIC_VECPRI_MASK |
|
|
(10 << MPIC_VECPRI_PRIORITY_SHIFT) |
|
|
(MPIC_VEC_IPI_0 + i));
|
|
#ifdef CONFIG_SMP
|
|
if (!(mpic->flags & MPIC_PRIMARY))
|
|
continue;
|
|
irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
|
|
irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
|
|
#endif /* CONFIG_SMP */
|
|
}
|
|
|
|
/* Initialize interrupt sources */
|
|
if (mpic->irq_count == 0)
|
|
mpic->irq_count = mpic->num_sources;
|
|
|
|
#ifdef CONFIG_MPIC_BROKEN_U3
|
|
/* Do the HT PIC fixups on U3 broken mpic */
|
|
DBG("MPIC flags: %x\n", mpic->flags);
|
|
if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
|
|
mpic_scan_ht_pics(mpic);
|
|
#endif /* CONFIG_MPIC_BROKEN_U3 */
|
|
|
|
for (i = 0; i < mpic->num_sources; i++) {
|
|
/* start with vector = source number, and masked */
|
|
u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
|
|
int level = 0;
|
|
|
|
/* if it's an IPI, we skip it */
|
|
if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
|
|
(mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
|
|
continue;
|
|
|
|
/* do senses munging */
|
|
if (mpic->senses && i < mpic->senses_count) {
|
|
if (mpic->senses[i] & IRQ_SENSE_LEVEL)
|
|
vecpri |= MPIC_VECPRI_SENSE_LEVEL;
|
|
if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
|
|
vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
|
|
} else
|
|
vecpri |= MPIC_VECPRI_SENSE_LEVEL;
|
|
|
|
/* remember if it was a level interrupts */
|
|
level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
|
|
|
|
/* deal with broken U3 */
|
|
if (mpic->flags & MPIC_BROKEN_U3) {
|
|
#ifdef CONFIG_MPIC_BROKEN_U3
|
|
if (mpic_is_ht_interrupt(mpic, i)) {
|
|
vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
|
|
MPIC_VECPRI_POLARITY_MASK);
|
|
vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
|
|
}
|
|
#else
|
|
printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
|
|
#endif
|
|
}
|
|
|
|
DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
|
|
(level != 0));
|
|
|
|
/* init hw */
|
|
mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
|
|
mpic_irq_write(i, MPIC_IRQ_DESTINATION,
|
|
1 << hard_smp_processor_id());
|
|
|
|
/* init linux descriptors */
|
|
if (i < mpic->irq_count) {
|
|
irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
|
|
irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
|
|
}
|
|
}
|
|
|
|
/* Init spurrious vector */
|
|
mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
|
|
|
|
/* Disable 8259 passthrough */
|
|
mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
|
|
mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
|
|
| MPIC_GREG_GCONF_8259_PTHROU_DIS);
|
|
|
|
/* Set current processor priority to 0 */
|
|
mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
|
|
}
|
|
|
|
void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
|
|
{
|
|
u32 v;
|
|
|
|
v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
|
|
v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
|
|
v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
|
|
mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
|
|
}
|
|
|
|
void __init mpic_set_serial_int(struct mpic *mpic, int enable)
|
|
{
|
|
u32 v;
|
|
|
|
v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
|
|
if (enable)
|
|
v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
|
|
else
|
|
v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
|
|
mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
|
|
}
|
|
|
|
void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
|
|
{
|
|
int is_ipi;
|
|
struct mpic *mpic = mpic_find(irq, &is_ipi);
|
|
unsigned long flags;
|
|
u32 reg;
|
|
|
|
spin_lock_irqsave(&mpic_lock, flags);
|
|
if (is_ipi) {
|
|
reg = mpic_ipi_read(irq - mpic->ipi_offset) &
|
|
~MPIC_VECPRI_PRIORITY_MASK;
|
|
mpic_ipi_write(irq - mpic->ipi_offset,
|
|
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
|
|
} else {
|
|
reg = mpic_irq_read(irq - mpic->irq_offset,MPIC_IRQ_VECTOR_PRI)
|
|
& ~MPIC_VECPRI_PRIORITY_MASK;
|
|
mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
|
|
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
|
|
}
|
|
spin_unlock_irqrestore(&mpic_lock, flags);
|
|
}
|
|
|
|
unsigned int mpic_irq_get_priority(unsigned int irq)
|
|
{
|
|
int is_ipi;
|
|
struct mpic *mpic = mpic_find(irq, &is_ipi);
|
|
unsigned long flags;
|
|
u32 reg;
|
|
|
|
spin_lock_irqsave(&mpic_lock, flags);
|
|
if (is_ipi)
|
|
reg = mpic_ipi_read(irq - mpic->ipi_offset);
|
|
else
|
|
reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
|
|
spin_unlock_irqrestore(&mpic_lock, flags);
|
|
return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
|
|
}
|
|
|
|
void mpic_setup_this_cpu(void)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
struct mpic *mpic = mpic_primary;
|
|
unsigned long flags;
|
|
u32 msk = 1 << hard_smp_processor_id();
|
|
unsigned int i;
|
|
|
|
BUG_ON(mpic == NULL);
|
|
|
|
DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
|
|
|
|
spin_lock_irqsave(&mpic_lock, flags);
|
|
|
|
/* let the mpic know we want intrs. default affinity is 0xffffffff
|
|
* until changed via /proc. That's how it's done on x86. If we want
|
|
* it differently, then we should make sure we also change the default
|
|
* values of irq_affinity in irq.c.
|
|
*/
|
|
if (distribute_irqs) {
|
|
for (i = 0; i < mpic->num_sources ; i++)
|
|
mpic_irq_write(i, MPIC_IRQ_DESTINATION,
|
|
mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
|
|
}
|
|
|
|
/* Set current processor priority to 0 */
|
|
mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
|
|
|
|
spin_unlock_irqrestore(&mpic_lock, flags);
|
|
#endif /* CONFIG_SMP */
|
|
}
|
|
|
|
int mpic_cpu_get_priority(void)
|
|
{
|
|
struct mpic *mpic = mpic_primary;
|
|
|
|
return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
|
|
}
|
|
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void mpic_cpu_set_priority(int prio)
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{
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struct mpic *mpic = mpic_primary;
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|
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prio &= MPIC_CPU_TASKPRI_MASK;
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mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
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}
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/*
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* XXX: someone who knows mpic should check this.
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* do we need to eoi the ipi including for kexec cpu here (see xics comments)?
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* or can we reset the mpic in the new kernel?
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*/
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void mpic_teardown_this_cpu(int secondary)
|
|
{
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|
struct mpic *mpic = mpic_primary;
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unsigned long flags;
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u32 msk = 1 << hard_smp_processor_id();
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unsigned int i;
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|
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BUG_ON(mpic == NULL);
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|
|
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DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
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spin_lock_irqsave(&mpic_lock, flags);
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|
|
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/* let the mpic know we don't want intrs. */
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for (i = 0; i < mpic->num_sources ; i++)
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mpic_irq_write(i, MPIC_IRQ_DESTINATION,
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mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
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|
|
|
/* Set current processor priority to max */
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mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
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|
|
|
spin_unlock_irqrestore(&mpic_lock, flags);
|
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}
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|
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|
|
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void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
|
|
{
|
|
struct mpic *mpic = mpic_primary;
|
|
|
|
BUG_ON(mpic == NULL);
|
|
|
|
#ifdef DEBUG_IPI
|
|
DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
|
|
#endif
|
|
|
|
mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
|
|
mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
|
|
}
|
|
|
|
int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
|
|
{
|
|
u32 irq;
|
|
|
|
irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
|
|
#ifdef DEBUG_LOW
|
|
DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
|
|
#endif
|
|
if (mpic->cascade && irq == mpic->cascade_vec) {
|
|
#ifdef DEBUG_LOW
|
|
DBG("%s: cascading ...\n", mpic->name);
|
|
#endif
|
|
irq = mpic->cascade(regs, mpic->cascade_data);
|
|
mpic_eoi(mpic);
|
|
return irq;
|
|
}
|
|
if (unlikely(irq == MPIC_VEC_SPURRIOUS))
|
|
return -1;
|
|
if (irq < MPIC_VEC_IPI_0) {
|
|
#ifdef DEBUG_IRQ
|
|
DBG("%s: irq %d\n", mpic->name, irq + mpic->irq_offset);
|
|
#endif
|
|
return irq + mpic->irq_offset;
|
|
}
|
|
#ifdef DEBUG_IPI
|
|
DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
|
|
#endif
|
|
return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
|
|
}
|
|
|
|
int mpic_get_irq(struct pt_regs *regs)
|
|
{
|
|
struct mpic *mpic = mpic_primary;
|
|
|
|
BUG_ON(mpic == NULL);
|
|
|
|
return mpic_get_one_irq(mpic, regs);
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
void mpic_request_ipis(void)
|
|
{
|
|
struct mpic *mpic = mpic_primary;
|
|
|
|
BUG_ON(mpic == NULL);
|
|
|
|
printk("requesting IPIs ... \n");
|
|
|
|
/* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
|
|
request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT,
|
|
"IPI0 (call function)", mpic);
|
|
request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT,
|
|
"IPI1 (reschedule)", mpic);
|
|
request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT,
|
|
"IPI2 (unused)", mpic);
|
|
request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT,
|
|
"IPI3 (debugger break)", mpic);
|
|
|
|
printk("IPIs requested... \n");
|
|
}
|
|
|
|
void smp_mpic_message_pass(int target, int msg)
|
|
{
|
|
/* make sure we're sending something that translates to an IPI */
|
|
if ((unsigned int)msg > 3) {
|
|
printk("SMP %d: smp_message_pass: unknown msg %d\n",
|
|
smp_processor_id(), msg);
|
|
return;
|
|
}
|
|
switch (target) {
|
|
case MSG_ALL:
|
|
mpic_send_ipi(msg, 0xffffffff);
|
|
break;
|
|
case MSG_ALL_BUT_SELF:
|
|
mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
|
|
break;
|
|
default:
|
|
mpic_send_ipi(msg, 1 << target);
|
|
break;
|
|
}
|
|
}
|
|
#endif /* CONFIG_SMP */
|