a019f4a9a7
Patch from Ben Dooks Move the decoding of the IRQ_EXT4 and above out of the entry macro, and into an chained irq handler as the EXTINT registers move depending on the CPU being used. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
51 lines
1.7 KiB
C
51 lines
1.7 KiB
C
/* linux/include/asm/arch-s3c2410/regs-irq.h
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*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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*
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* Changelog:
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* 19-06-2003 BJD Created file
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* 12-03-2004 BJD Updated include protection
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* 10-03-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
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*/
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#ifndef ___ASM_ARCH_REGS_IRQ_H
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#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
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/* interrupt controller */
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#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
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#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
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#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
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#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
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#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
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#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
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#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
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#define S3C2410_INTPND S3C2410_IRQREG(0x010)
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#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
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#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
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#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
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/* mask: 0=enable, 1=disable
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* 1 bit EINT, 4=EINT4, 23=EINT23
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* EINT0,1,2,3 are not handled here.
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*/
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#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
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#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
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#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
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#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
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#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
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#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
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#endif /* ___ASM_ARCH_REGS_IRQ_H */
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