1b3c5cdab4
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
375 lines
8.0 KiB
Plaintext
375 lines
8.0 KiB
Plaintext
/*
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* MPC8544 DS Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8544DS";
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compatible = "MPC8544DS", "MPC85xxDS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8544@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 00000000>; // Filled by U-Boot
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};
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soc8544@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <00000000 e0000000 00100000>;
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reg = <e0000000 00001000>; // CCSRBAR 1M
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bus-frequency = <0>; // Filled out by uboot.
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memory-controller@2000 {
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compatible = "fsl,8544-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <12 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8544-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <10 2>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <a 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <a 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <26000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1f 2 20 2 21 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8548-guts";
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reg = <e0000 1000>;
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fsl,has-rstcr;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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};
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pci@e0008000 {
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 J17 Slot 1 */
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8800 0 0 1 &mpic 2 1
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8800 0 0 2 &mpic 3 1
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8800 0 0 3 &mpic 4 1
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8800 0 0 4 &mpic 1 1
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/* IDSEL 0x12 J16 Slot 2 */
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9000 0 0 1 &mpic 3 1
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9000 0 0 2 &mpic 4 1
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9000 0 0 3 &mpic 2 1
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9000 0 0 4 &mpic 1 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 ff>;
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ranges = <02000000 0 c0000000 c0000000 0 20000000
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01000000 0 00000000 e1000000 0 00010000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008000 1000>;
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};
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pcie@e0009000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0009000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e1010000 0 00010000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <1a 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 4 1
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0000 0 0 2 &mpic 5 1
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0000 0 0 3 &mpic 6 1
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0000 0 0 4 &mpic 7 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00010000>;
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};
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};
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pcie@e000a000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e000a000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 e1020000 0 00010000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 a0000000
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02000000 0 a0000000
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0 10000000
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01000000 0 00000000
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01000000 0 00000000
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0 00010000>;
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};
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};
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pcie@e000b000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e000b000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 b0000000 b0000000 0 00100000
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01000000 0 00000000 b0100000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <1b 2>;
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interrupt-map-mask = <fb00 0 0 0>;
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interrupt-map = <
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// IDSEL 0x1c USB
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e000 0 0 0 &i8259 c 2
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e100 0 0 0 &i8259 9 2
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e200 0 0 0 &i8259 a 2
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e300 0 0 0 &i8259 b 2
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// IDSEL 0x1d Audio
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e800 0 0 0 &i8259 6 2
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// IDSEL 0x1e Legacy
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f000 0 0 0 &i8259 7 2
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f100 0 0 0 &i8259 7 2
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// IDSEL 0x1f IDE/SATA
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f800 0 0 0 &i8259 e 2
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f900 0 0 0 &i8259 5 2
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 b0000000
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02000000 0 b0000000
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0 00100000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 b0000000
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02000000 0 b0000000
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0 00100000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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isa@1e {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <f000 0 0 0 0>;
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ranges = <1 0
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01000000 0 0
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00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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interrupt-controller;
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device_type = "interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <9 2>;
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interrupt-parent = <&mpic>;
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};
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i8042@60 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <1 60 1 1 64 1>;
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interrupts = <1 3 c 3>;
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interrupt-parent = <&i8259>;
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keyboard@0 {
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reg = <0>;
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compatible = "pnpPNP,303";
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};
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mouse@1 {
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reg = <1>;
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compatible = "pnpPNP,f03";
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};
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <1 70 2>;
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};
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gpio@400 {
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reg = <1 400 80>;
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};
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};
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};
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};
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};
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};
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