1d4c452a85
Since irq.c uses smp_send_all_nop, we must define it for UP builds as well. Make it a static inline so it gets optimized away. This forces irq.c to include <asm/smp.h> though. Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
75 lines
1.7 KiB
C
75 lines
1.7 KiB
C
#ifndef __ASM_SMP_H
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#define __ASM_SMP_H
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#include <linux/config.h>
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#if defined(CONFIG_SMP)
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/* Page Zero Location PDC will look for the address to branch to when we poke
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** slave CPUs still in "Icache loop".
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*/
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#define PDC_OS_BOOT_RENDEZVOUS 0x10
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#define PDC_OS_BOOT_RENDEZVOUS_HI 0x28
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#ifndef ASSEMBLY
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#include <linux/bitops.h>
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#include <linux/threads.h> /* for NR_CPUS */
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#include <linux/cpumask.h>
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typedef unsigned long address_t;
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extern cpumask_t cpu_online_map;
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/*
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* Private routines/data
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*
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* physical and logical are equivalent until we support CPU hotplug.
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*/
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#define cpu_number_map(cpu) (cpu)
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#define cpu_logical_map(cpu) (cpu)
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extern void smp_send_reschedule(int cpu);
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extern void smp_send_all_nop(void);
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#endif /* !ASSEMBLY */
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/*
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* This magic constant controls our willingness to transfer
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* a process across CPUs. Such a transfer incurs cache and tlb
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* misses. The current value is inherited from i386. Still needs
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* to be tuned for parisc.
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*/
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#define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
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#undef ENTRY_SYS_CPUS
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#ifdef ENTRY_SYS_CPUS
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#define STATE_RENDEZVOUS 0
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#define STATE_STOPPED 1
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#define STATE_RUNNING 2
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#define STATE_HALTED 3
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#endif
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extern unsigned long cpu_present_mask;
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#define raw_smp_processor_id() (current_thread_info()->cpu)
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#else /* CONFIG_SMP */
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static inline void smp_send_all_nop(void) { return; }
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#endif
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#define NO_PROC_ID 0xFF /* No processor magic marker */
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#define ANY_PROC_ID 0xFF /* Any processor magic marker */
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static inline int __cpu_disable (void) {
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return 0;
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}
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static inline void __cpu_die (unsigned int cpu) {
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while(1)
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;
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}
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extern int __cpu_up (unsigned int cpu);
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#endif /* __ASM_SMP_H */
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