041a89a419
Make the ColdFire 5249 MBAR peripheral register definitions absolute addresses, instead of offsets into the region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
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* intc2.c -- support for the 2nd INTC controller of the 5249
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*
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* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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static void intc2_irq_gpio_mask(struct irq_data *d)
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{
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u32 imr;
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imr = readl(MCFSIM2_GPIOINTENABLE);
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imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
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writel(imr, MCFSIM2_GPIOINTENABLE);
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}
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static void intc2_irq_gpio_unmask(struct irq_data *d)
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{
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u32 imr;
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imr = readl(MCFSIM2_GPIOINTENABLE);
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imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
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writel(imr, MCFSIM2_GPIOINTENABLE);
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}
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static void intc2_irq_gpio_ack(struct irq_data *d)
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{
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writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
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}
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static struct irq_chip intc2_irq_gpio_chip = {
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.name = "CF-INTC2",
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.irq_mask = intc2_irq_gpio_mask,
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.irq_unmask = intc2_irq_gpio_unmask,
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.irq_ack = intc2_irq_gpio_ack,
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};
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static int __init mcf_intc2_init(void)
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{
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int irq;
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/* GPIO interrupt sources */
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for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
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irq_set_chip(irq, &intc2_irq_gpio_chip);
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irq_set_handler(irq, handle_edge_irq);
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}
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return 0;
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}
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arch_initcall(mcf_intc2_init);
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