bbdea849ed
The ColdFire M54xx SoC family have a traditional PCI bus interface. Add the core support code to access and use this bus on these parts. This code provides all the config space access functions and IO access functions. It also carries out the PCI bus initialization and hooks into the kernel PCI subsystem. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
42 lines
1.5 KiB
Makefile
42 lines
1.5 KiB
Makefile
#
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# Makefile for the m68knommu kernel.
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#
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#
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# If you want to play with the HW breakpoints then you will
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# need to add define this, which will give you a stack backtrace
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# on the console port whenever a DBG interrupt occurs. You have to
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# set up you HW breakpoints to trigger a DBG interrupt:
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#
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# ccflags-y := -DTRAP_DBG_INTERRUPT
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# asflags-y := -DTRAP_DBG_INTERRUPT
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#
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asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
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obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o
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obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
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obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
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obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
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obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
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obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
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obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
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obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
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obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
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obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
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obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
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obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
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obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
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obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
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obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
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obj-$(CONFIG_NETtel) += nettel.o
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obj-$(CONFIG_CLEOPATRA) += nettel.o
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obj-$(CONFIG_FIREBEE) += firebee.o
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obj-$(CONFIG_MCF8390) += mcf8390.o
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obj-$(CONFIG_PCI) += pci.o
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obj-y += gpio.o
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extra-y := head.o
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