ffaa8bd6c9
I believe at least for seccomp it's worth to turn off the tsc, not just for HT but for the L2 cache too. So it's up to you, either you turn it off completely (which isn't very nice IMHO) or I recommend to apply this below patch. This has been tested successfully on x86-64 against current cogito repository (i686 compiles so I didn't bother testing ;). People selling the cpu through cpushare may appreciate this bit for a peace of mind. There's no way to get any timing info anymore with this applied (gettimeofday is forbidden of course). The seccomp environment is completely deterministic so it can't be allowed to get timing info, it has to be deterministic so in the future I can enable a computing mode that does a parallel computing for each task with server side transparent checkpointing and verification that the output is the same from all the 2/3 seller computers for each task, without the buyer even noticing (for now the verification is left to the buyer client side and there's no checkpointing, since that would require more kernel changes to track the dirty bits but it'll be easy to extend once the basic mode is finished). Eliminating a cold-cache read of the cr4 global variable will save one cacheline during the tlb flush while making the code per-cpu-safe at the same time. Thanks to Mikael Pettersson for noticing the tlb flush wasn't per-cpu-safe. The global tlb flush can run from irq (IPI calling do_flush_tlb_all) but it'll be transparent to the switch_to code since the IPI won't make any change to the cr4 contents from the point of view of the interrupted code and since it's now all per-cpu stuff, it will not race. So no need to disable irqs in switch_to slow path. Signed-off-by: Andrea Arcangeli <andrea@cpushare.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
150 lines
3.7 KiB
C
150 lines
3.7 KiB
C
#ifndef _I386_TLBFLUSH_H
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#define _I386_TLBFLUSH_H
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#include <linux/config.h>
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#include <linux/mm.h>
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#include <asm/processor.h>
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#define __flush_tlb() \
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do { \
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unsigned int tmpreg; \
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\
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__asm__ __volatile__( \
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"movl %%cr3, %0; \n" \
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"movl %0, %%cr3; # flush TLB \n" \
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: "=r" (tmpreg) \
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:: "memory"); \
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} while (0)
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/*
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* Global pages have to be flushed a bit differently. Not a real
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* performance problem because this does not happen often.
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*/
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#define __flush_tlb_global() \
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do { \
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unsigned int tmpreg, cr4, cr4_orig; \
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\
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__asm__ __volatile__( \
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"movl %%cr4, %2; # turn off PGE \n" \
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"movl %2, %1; \n" \
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"andl %3, %1; \n" \
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"movl %1, %%cr4; \n" \
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"movl %%cr3, %0; \n" \
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"movl %0, %%cr3; # flush TLB \n" \
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"movl %2, %%cr4; # turn PGE back on \n" \
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: "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
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: "i" (~X86_CR4_PGE) \
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: "memory"); \
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} while (0)
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extern unsigned long pgkern_mask;
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# define __flush_tlb_all() \
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do { \
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if (cpu_has_pge) \
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__flush_tlb_global(); \
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else \
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__flush_tlb(); \
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} while (0)
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#define cpu_has_invlpg (boot_cpu_data.x86 > 3)
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#define __flush_tlb_single(addr) \
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__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
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#ifdef CONFIG_X86_INVLPG
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# define __flush_tlb_one(addr) __flush_tlb_single(addr)
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#else
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# define __flush_tlb_one(addr) \
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do { \
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if (cpu_has_invlpg) \
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__flush_tlb_single(addr); \
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else \
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__flush_tlb(); \
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} while (0)
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#endif
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/*
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* TLB flushing:
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*
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* - flush_tlb() flushes the current mm struct TLBs
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
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*
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* ..but the i386 has somewhat limited tlb flushing capabilities,
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* and page-granular flushes are available only on i486 and up.
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*/
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#ifndef CONFIG_SMP
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#define flush_tlb() __flush_tlb()
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#define flush_tlb_all() __flush_tlb_all()
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#define local_flush_tlb() __flush_tlb()
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (mm == current->active_mm)
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__flush_tlb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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#else
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#include <asm/smp.h>
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#define local_flush_tlb() \
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__flush_tlb()
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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extern void flush_tlb_mm(struct mm_struct *);
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extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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#define flush_tlb() flush_tlb_current_task()
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static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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struct tlb_state
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{
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struct mm_struct *active_mm;
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int state;
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char __cacheline_padding[L1_CACHE_BYTES-8];
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};
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DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
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#endif
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#define flush_tlb_kernel_range(start, end) flush_tlb_all()
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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/* i386 does not keep any page table caches in TLB */
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}
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#endif /* _I386_TLBFLUSH_H */
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