c78095bd8c
This code is used in other places in our system than in Linux, so to share it we now implement it as an inline function in our low-level <arch> headers, and instantiate it in one file in Linux's arch/tile/lib. The file is now cacheflush.c and is C code rather than the strangely-named and assembler-implemented __invalidate_icache.S. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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*/
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/**
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* @file
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*
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* Support for invalidating bytes in the instruction
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*/
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#ifndef __ARCH_ICACHE_H__
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#define __ARCH_ICACHE_H__
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#include <arch/chip.h>
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/**
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* Invalidate the instruction cache for the given range of memory.
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*
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* @param addr The start of memory to be invalidated.
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* @param size The number of bytes to be invalidated.
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* @param page_size The system's page size, typically the PAGE_SIZE constant
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* in sys/page.h. This value must be a power of two no larger
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* than the page containing the code to be invalidated. If the value
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* is smaller than the actual page size, this function will still
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* work, but may run slower than necessary.
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*/
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static __inline void
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invalidate_icache(const void* addr, unsigned long size,
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unsigned long page_size)
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{
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const unsigned long cache_way_size =
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CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
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unsigned long max_useful_size;
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const char* start, *end;
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long num_passes;
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if (__builtin_expect(size == 0, 0))
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return;
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#ifdef __tilegx__
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/* Limit the number of bytes visited to avoid redundant iterations. */
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max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
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/* No PA aliasing is possible, so one pass always suffices. */
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num_passes = 1;
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#else
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/* Limit the number of bytes visited to avoid redundant iterations. */
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max_useful_size = cache_way_size;
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/*
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* Compute how many passes we need (we'll treat 0 as if it were 1).
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* This works because we know the page size is a power of two.
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*/
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num_passes = cache_way_size >> __builtin_ctzl(page_size);
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#endif
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if (__builtin_expect(size > max_useful_size, 0))
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size = max_useful_size;
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/* Locate the first and last bytes to be invalidated. */
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start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
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end = (const char*)addr + size - 1;
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__insn_mf();
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do
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{
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const char* p;
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for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
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__insn_icoh(p);
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start += page_size;
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end += page_size;
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}
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while (--num_passes > 0);
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__insn_drain();
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}
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#endif /* __ARCH_ICACHE_H__ */
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