0868ff7a42
My first guess for "fujitsu" was it might be related to the fujitsu-laptop.c driver... Move the frv directory one level up since frv is the name of the architecture in the Linux kernel. Signed-off-by: Adrian Bunk <bunk@kernel.org>
174 lines
5.2 KiB
ArmAsm
174 lines
5.2 KiB
ArmAsm
/* atomic-ops.S: kernel atomic operations
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*
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* For an explanation of how atomic ops work in this arch, see:
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* Documentation/frv/atomic-ops.txt
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/spr-regs.h>
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.text
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.balign 4
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###############################################################################
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#
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# unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
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#
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###############################################################################
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.globl atomic_test_and_ANDNOT_mask
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.type atomic_test_and_ANDNOT_mask,@function
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atomic_test_and_ANDNOT_mask:
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not.p gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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and gr8,gr10,gr11
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cst.p gr11,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size atomic_test_and_ANDNOT_mask, .-atomic_test_and_ANDNOT_mask
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###############################################################################
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#
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# unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
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#
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###############################################################################
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.globl atomic_test_and_OR_mask
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.type atomic_test_and_OR_mask,@function
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atomic_test_and_OR_mask:
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or.p gr8,gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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or gr8,gr10,gr11
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cst.p gr11,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size atomic_test_and_OR_mask, .-atomic_test_and_OR_mask
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###############################################################################
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#
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# unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
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#
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###############################################################################
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.globl atomic_test_and_XOR_mask
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.type atomic_test_and_XOR_mask,@function
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atomic_test_and_XOR_mask:
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or.p gr8,gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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xor gr8,gr10,gr11
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cst.p gr11,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size atomic_test_and_XOR_mask, .-atomic_test_and_XOR_mask
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###############################################################################
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#
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# int atomic_add_return(int i, atomic_t *v)
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#
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###############################################################################
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.globl atomic_add_return
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.type atomic_add_return,@function
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atomic_add_return:
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or.p gr8,gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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add gr8,gr10,gr8
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cst.p gr8,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size atomic_add_return, .-atomic_add_return
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###############################################################################
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#
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# int atomic_sub_return(int i, atomic_t *v)
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#
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###############################################################################
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.globl atomic_sub_return
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.type atomic_sub_return,@function
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atomic_sub_return:
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or.p gr8,gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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sub gr8,gr10,gr8
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cst.p gr8,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size atomic_sub_return, .-atomic_sub_return
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###############################################################################
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#
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# uint32_t __xchg_32(uint32_t i, uint32_t *v)
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#
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###############################################################################
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.globl __xchg_32
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.type __xchg_32,@function
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__xchg_32:
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or.p gr8,gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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cst.p gr10,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size __xchg_32, .-__xchg_32
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###############################################################################
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#
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# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new)
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#
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###############################################################################
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.globl __cmpxchg_32
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.type __cmpxchg_32,@function
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__cmpxchg_32:
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or.p gr8,gr8,gr11
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0:
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orcc gr0,gr0,gr0,icc3
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ckeq icc3,cc7
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ld.p @(gr11,gr0),gr8
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orcr cc7,cc7,cc3
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subcc gr8,gr9,gr7,icc0
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bne icc0,#0,1f
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cst.p gr10,@(gr11,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1
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beq icc3,#0,0b
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1:
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bralr
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.size __cmpxchg_32, .-__cmpxchg_32
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