7dffb72028
instead of L1_CACHE_LINE_SIZE and LG_L1_CACHE_LINE_SIZE Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
199 lines
3.8 KiB
ArmAsm
199 lines
3.8 KiB
ArmAsm
/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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_GLOBAL(__970_cpu_preinit)
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/*
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* Deal only with PPC970 and PPC970FX.
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*/
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi cr0,r0,0x39
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cmpwi cr1,r0,0x3c
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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bnelr
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/* Make sure HID4:rm_ci is off before MMU is turned off, that large
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* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
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* HID5:DCBZ32_ill
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*/
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li r0,0
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mfspr r11,SPRN_HID4
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rldimi r11,r0,40,23 /* clear bit 23 (rm_ci) */
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rldimi r11,r0,2,61 /* clear bit 61 (lg_pg_en) */
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sync
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mtspr SPRN_HID4,r11
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isync
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sync
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mfspr r11,SPRN_HID5
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rldimi r11,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
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sync
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mtspr SPRN_HID5,r11
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isync
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sync
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/* Setup some basic HID1 features */
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mfspr r0,SPRN_HID1
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li r11,0x1200 /* enable i-fetch cacheability */
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sldi r11,r11,44 /* and prefetch */
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or r0,r0,r11
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mtspr SPRN_HID1,r0
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mtspr SPRN_HID1,r0
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isync
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/* Clear HIOR */
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li r0,0
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sync
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mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
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isync
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blr
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_GLOBAL(__setup_cpu_ppc970)
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mfspr r0,SPRN_HID0
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li r11,5 /* clear DOZE and SLEEP */
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rldimi r0,r11,52,8 /* set NAP and DPM */
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mtspr SPRN_HID0,r0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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sync
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isync
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blr
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/* Definitions for the table use to save CPU states */
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#define CS_HID0 0
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#define CS_HID1 8
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#define CS_HID4 16
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#define CS_HID5 24
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#define CS_SIZE 32
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.data
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.balign L1_CACHE_BYTES
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cpu_state_storage:
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.space CS_SIZE
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.balign L1_CACHE_BYTES,0
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.text
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/* Called in normal context to backup CPU 0 state. This
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* does not include cache settings. This function is also
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* called for machine sleep. This does not include the MMU
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* setup, BATs, etc... but rather the "special" registers
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* like HID0, HID1, HID4, etc...
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*/
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_GLOBAL(__save_cpu_setup)
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/* Some CR fields are volatile, we back it up all */
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mfcr r7
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/* Get storage ptr */
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lis r5,cpu_state_storage@h
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ori r5,r5,cpu_state_storage@l
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/* We only deal with 970 for now */
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi cr0,r0,0x39
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cmpwi cr1,r0,0x3c
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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bne 1f
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/* Save HID0,1,4 and 5 */
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mfspr r3,SPRN_HID0
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std r3,CS_HID0(r5)
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mfspr r3,SPRN_HID1
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std r3,CS_HID1(r5)
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mfspr r3,SPRN_HID4
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std r3,CS_HID4(r5)
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mfspr r3,SPRN_HID5
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std r3,CS_HID5(r5)
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1:
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mtcr r7
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blr
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/* Called with no MMU context (typically MSR:IR/DR off) to
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* restore CPU state as backed up by the previous
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* function. This does not include cache setting
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*/
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_GLOBAL(__restore_cpu_setup)
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/* Some CR fields are volatile, we back it up all */
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mfcr r7
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/* Get storage ptr */
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lis r5,(cpu_state_storage-KERNELBASE)@h
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ori r5,r5,cpu_state_storage@l
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/* We only deal with 970 for now */
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi cr0,r0,0x39
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cmpwi cr1,r0,0x3c
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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bne 1f
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/* Clear interrupt prefix */
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li r0,0
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sync
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mtspr SPRN_HIOR,0
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isync
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/* Restore HID0 */
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ld r3,CS_HID0(r5)
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sync
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isync
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mtspr SPRN_HID0,r3
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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sync
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isync
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/* Restore HID1 */
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ld r3,CS_HID1(r5)
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sync
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isync
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mtspr SPRN_HID1,r3
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mtspr SPRN_HID1,r3
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sync
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isync
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/* Restore HID4 */
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ld r3,CS_HID4(r5)
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sync
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isync
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mtspr SPRN_HID4,r3
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sync
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isync
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/* Restore HID5 */
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ld r3,CS_HID5(r5)
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sync
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isync
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mtspr SPRN_HID5,r3
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sync
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isync
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1:
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mtcr r7
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blr
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