Ben Skeggs 79eee7aa0d drm/nvc0/ltcg: mask off intr 0x10 ... NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10 intrs we receive are normal and we can ignore them. On Kepler NVIDIA *don't* do this, but the hardware appears to come up with the bit masked off by default - so that's probably why :) This should silence some interrupt spam seen on Fermi+ boards. Backported patch from reworked nouveau kernel tree. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2012-09-26 12:43:10 +10:00
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drm	drm/nvc0/ltcg: mask off intr 0x10	2012-09-26 12:43:10 +10:00
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vga	vga_switcheroo: Don't require handler init callback	2012-08-17 17:34:41 -04:00
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