2cf46c636f
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/6c5948373d309408095c1a098b7b4c491c5265f7.1672490071.git.christophe.jaillet@wanadoo.fr Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
218 lines
5.8 KiB
C
218 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#define DEFAULT_TIMEOUT 30 /* seconds */
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#define GXBB_WDT_CTRL_REG 0x0
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#define GXBB_WDT_TCNT_REG 0x8
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#define GXBB_WDT_RSET_REG 0xc
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#define GXBB_WDT_CTRL_CLKDIV_EN BIT(25)
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#define GXBB_WDT_CTRL_CLK_EN BIT(24)
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#define GXBB_WDT_CTRL_EE_RESET BIT(21)
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#define GXBB_WDT_CTRL_EN BIT(18)
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#define GXBB_WDT_CTRL_DIV_MASK (BIT(18) - 1)
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#define GXBB_WDT_TCNT_SETUP_MASK (BIT(16) - 1)
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#define GXBB_WDT_TCNT_CNT_SHIFT 16
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static unsigned int timeout;
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module_param(timeout, uint, 0);
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MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds="
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__MODULE_STRING(DEFAULT_TIMEOUT) ")");
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struct meson_gxbb_wdt {
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void __iomem *reg_base;
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struct watchdog_device wdt_dev;
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struct clk *clk;
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};
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static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev)
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{
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struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
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writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
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data->reg_base + GXBB_WDT_CTRL_REG);
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return 0;
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}
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static int meson_gxbb_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
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writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
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data->reg_base + GXBB_WDT_CTRL_REG);
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return 0;
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}
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static int meson_gxbb_wdt_ping(struct watchdog_device *wdt_dev)
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{
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struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
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writel(0, data->reg_base + GXBB_WDT_RSET_REG);
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return 0;
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}
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static int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int timeout)
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{
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struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
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unsigned long tcnt = timeout * 1000;
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if (tcnt > GXBB_WDT_TCNT_SETUP_MASK)
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tcnt = GXBB_WDT_TCNT_SETUP_MASK;
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wdt_dev->timeout = timeout;
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meson_gxbb_wdt_ping(wdt_dev);
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writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
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return 0;
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}
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static unsigned int meson_gxbb_wdt_get_timeleft(struct watchdog_device *wdt_dev)
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{
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struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
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unsigned long reg;
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reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
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return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
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(reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
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}
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static const struct watchdog_ops meson_gxbb_wdt_ops = {
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.start = meson_gxbb_wdt_start,
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.stop = meson_gxbb_wdt_stop,
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.ping = meson_gxbb_wdt_ping,
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.set_timeout = meson_gxbb_wdt_set_timeout,
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.get_timeleft = meson_gxbb_wdt_get_timeleft,
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};
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static const struct watchdog_info meson_gxbb_wdt_info = {
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.identity = "Meson GXBB Watchdog",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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};
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static int __maybe_unused meson_gxbb_wdt_resume(struct device *dev)
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{
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struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
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if (watchdog_active(&data->wdt_dev))
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meson_gxbb_wdt_start(&data->wdt_dev);
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return 0;
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}
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static int __maybe_unused meson_gxbb_wdt_suspend(struct device *dev)
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{
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struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
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if (watchdog_active(&data->wdt_dev))
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meson_gxbb_wdt_stop(&data->wdt_dev);
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return 0;
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}
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static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume)
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};
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static const struct of_device_id meson_gxbb_wdt_dt_ids[] = {
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{ .compatible = "amlogic,meson-gxbb-wdt", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids);
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static int meson_gxbb_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct meson_gxbb_wdt *data;
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u32 ctrl_reg;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->reg_base))
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return PTR_ERR(data->reg_base);
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data->clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(data->clk))
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return PTR_ERR(data->clk);
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platform_set_drvdata(pdev, data);
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data->wdt_dev.parent = dev;
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data->wdt_dev.info = &meson_gxbb_wdt_info;
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data->wdt_dev.ops = &meson_gxbb_wdt_ops;
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data->wdt_dev.max_hw_heartbeat_ms = GXBB_WDT_TCNT_SETUP_MASK;
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data->wdt_dev.min_timeout = 1;
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data->wdt_dev.timeout = DEFAULT_TIMEOUT;
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watchdog_init_timeout(&data->wdt_dev, timeout, dev);
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watchdog_set_nowayout(&data->wdt_dev, nowayout);
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watchdog_set_drvdata(&data->wdt_dev, data);
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ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) &
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GXBB_WDT_CTRL_EN;
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if (ctrl_reg) {
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/* Watchdog is running - keep it running but extend timeout
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* to the maximum while setting the timebase
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*/
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set_bit(WDOG_HW_RUNNING, &data->wdt_dev.status);
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meson_gxbb_wdt_set_timeout(&data->wdt_dev,
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GXBB_WDT_TCNT_SETUP_MASK / 1000);
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}
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/* Setup with 1ms timebase */
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ctrl_reg |= ((clk_get_rate(data->clk) / 1000) &
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GXBB_WDT_CTRL_DIV_MASK) |
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GXBB_WDT_CTRL_EE_RESET |
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GXBB_WDT_CTRL_CLK_EN |
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GXBB_WDT_CTRL_CLKDIV_EN;
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writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);
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meson_gxbb_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
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return devm_watchdog_register_device(dev, &data->wdt_dev);
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}
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static struct platform_driver meson_gxbb_wdt_driver = {
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.probe = meson_gxbb_wdt_probe,
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.driver = {
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.name = "meson-gxbb-wdt",
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.pm = &meson_gxbb_wdt_pm_ops,
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.of_match_table = meson_gxbb_wdt_dt_ids,
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},
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};
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module_platform_driver(meson_gxbb_wdt_driver);
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_DESCRIPTION("Amlogic Meson GXBB Watchdog timer driver");
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MODULE_LICENSE("Dual BSD/GPL");
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