3042102a28
- core header files for arch-msm - Kconfig and Makefiles to enable ARCH_MSM7X00A builds - MSM7X00A specific arch_idle - peripheral iomap and irq number definitions Signed-off-by: Brian Swetland <swetland@google.com>
105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
/* linux/include/asm-arm/arch-msm/msm_iomap.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* The MSM peripherals are spread all over across 768MB of physical
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* space, which makes just having a simple IO_ADDRESS macro to slide
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* them into the right virtual location rough. Instead, we will
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* provide a master phys->virt mapping for peripherals here.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IOMAP_H
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#define __ASM_ARCH_MSM_IOMAP_H
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#include <asm/sizes.h>
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/* Physical base address and size of peripherals.
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* Ordered by the virtual base addresses they will be mapped at.
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*
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* MSM_VIC_BASE must be an value that can be loaded via a "mov"
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* instruction, otherwise entry-macro.S will not compile.
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*
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* If you add or remove entries here, you'll want to edit the
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* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
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* changes.
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*
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*/
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#define MSM_VIC_BASE 0xE0000000
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#define MSM_VIC_PHYS 0xC0000000
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#define MSM_VIC_SIZE SZ_4K
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#define MSM_CSR_BASE 0xE0001000
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#define MSM_CSR_PHYS 0xC0100000
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#define MSM_CSR_SIZE SZ_4K
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#define MSM_GPT_PHYS MSM_CSR_PHYS
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#define MSM_GPT_BASE MSM_CSR_BASE
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#define MSM_GPT_SIZE SZ_4K
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#define MSM_DMOV_BASE 0xE0002000
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#define MSM_DMOV_PHYS 0xA9700000
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#define MSM_DMOV_SIZE SZ_4K
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#define MSM_UART1_BASE 0xE0003000
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#define MSM_UART1_PHYS 0xA9A00000
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#define MSM_UART1_SIZE SZ_4K
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#define MSM_UART2_BASE 0xE0004000
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#define MSM_UART2_PHYS 0xA9B00000
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#define MSM_UART2_SIZE SZ_4K
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#define MSM_UART3_BASE 0xE0005000
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#define MSM_UART3_PHYS 0xA9C00000
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#define MSM_UART3_SIZE SZ_4K
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#define MSM_I2C_BASE 0xE0006000
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#define MSM_I2C_PHYS 0xA9900000
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#define MSM_I2C_SIZE SZ_4K
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#define MSM_GPIO1_BASE 0xE0007000
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#define MSM_GPIO1_PHYS 0xA9200000
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#define MSM_GPIO1_SIZE SZ_4K
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#define MSM_GPIO2_BASE 0xE0008000
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#define MSM_GPIO2_PHYS 0xA9300000
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#define MSM_GPIO2_SIZE SZ_4K
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#define MSM_HSUSB_BASE 0xE0009000
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#define MSM_HSUSB_PHYS 0xA0800000
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#define MSM_HSUSB_SIZE SZ_4K
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#define MSM_CLK_CTL_BASE 0xE000A000
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#define MSM_CLK_CTL_PHYS 0xA8600000
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#define MSM_CLK_CTL_SIZE SZ_4K
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#define MSM_PMDH_BASE 0xE000B000
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#define MSM_PMDH_PHYS 0xAA600000
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#define MSM_PMDH_SIZE SZ_4K
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#define MSM_EMDH_BASE 0xE000C000
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#define MSM_EMDH_PHYS 0xAA700000
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#define MSM_EMDH_SIZE SZ_4K
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#define MSM_MDP_BASE 0xE0010000
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#define MSM_MDP_PHYS 0xAA200000
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#define MSM_MDP_SIZE 0x000F0000
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#define MSM_SHARED_RAM_BASE 0xE0100000
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#define MSM_SHARED_RAM_PHYS 0x01F00000
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#define MSM_SHARED_RAM_SIZE SZ_1M
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#endif
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