4a7b98d7e7
mxc_iomux_set_pad() is buggy on i.MX31 - it calculates the register and the offset therein wrongly. Fix it. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
115 lines
2.9 KiB
C
115 lines
2.9 KiB
C
/*
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* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <mach/gpio.h>
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#include <mach/iomux-mx3.h>
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/*
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* IOMUX register (base) addresses
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*/
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#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
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#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
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#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
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#define IOMUXGPR (IOMUX_BASE + 0x008)
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#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
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#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
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static DEFINE_SPINLOCK(gpio_mux_lock);
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#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
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/*
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* set the mode for a IOMUX pin.
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*/
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int mxc_iomux_mode(unsigned int pin_mode)
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{
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u32 field, l, mode, ret = 0;
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void __iomem *reg;
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reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
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field = pin_mode & 0x3;
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mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
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pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
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__func__, (pin_mode & IOMUX_REG_MASK), field, mode);
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spin_lock(&gpio_mux_lock);
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l = __raw_readl(reg);
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l &= ~(0xff << (field * 8));
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l |= mode << (field * 8);
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__raw_writel(l, reg);
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spin_unlock(&gpio_mux_lock);
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return ret;
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}
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EXPORT_SYMBOL(mxc_iomux_mode);
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/*
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* This function configures the pad value for a IOMUX pin.
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*/
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void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
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{
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u32 field, l;
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void __iomem *reg;
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pin &= IOMUX_PADNUM_MASK;
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reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
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field = (pin + 2) % 3;
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pr_debug("%s: reg offset = 0x%x, field = %d\n",
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__func__, (pin + 2) / 3, field);
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spin_lock(&gpio_mux_lock);
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l = __raw_readl(reg);
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l &= ~(0x1ff << (field * 10));
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l |= config << (field * 10);
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__raw_writel(l, reg);
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spin_unlock(&gpio_mux_lock);
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}
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EXPORT_SYMBOL(mxc_iomux_set_pad);
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/*
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* This function enables/disables the general purpose function for a particular
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* signal.
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*/
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void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
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{
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u32 l;
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spin_lock(&gpio_mux_lock);
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l = __raw_readl(IOMUXGPR);
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if (en)
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l |= gp;
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else
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l &= ~gp;
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__raw_writel(l, IOMUXGPR);
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spin_unlock(&gpio_mux_lock);
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}
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EXPORT_SYMBOL(mxc_iomux_set_gpr);
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