e465058d55
This patch hooks Calgary into the build, the x86-64 IOMMU initialization paths, and introduces the Calgary specific bits. The implementation draws inspiration from both PPC (which has support for the same chip but requires firmware support which we don't have on x86-64) and gart. Calgary is different from gart in that it support a translation table per PHB, as opposed to the single gart aperture. Changes from previous version: * Addition of boot-time disablement for bus-level translation/isolation (e.g, enable userspace DMA for things like X) * Usage of newer IOMMU abstraction functions Signed-off-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Jon Mason <jdmason@us.ibm.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
/*
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* Copyright (C) 2006 Muli Ben-Yehuda <muli@il.ibm.com>, IBM Corporation
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* Copyright (C) 2006 Jon Mason <jdmason@us.ibm.com>, IBM Corporation
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*
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* This file is derived from asm-powerpc/tce.h.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_X86_64_TCE_H
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#define _ASM_X86_64_TCE_H
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extern void* tce_table_kva[];
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extern unsigned int specified_table_size;
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struct iommu_table;
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#define TCE_ENTRY_SIZE 8 /* in bytes */
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#define TCE_READ_SHIFT 0
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#define TCE_WRITE_SHIFT 1
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#define TCE_HUBID_SHIFT 2 /* unused */
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#define TCE_RSVD_SHIFT 8 /* unused */
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#define TCE_RPN_SHIFT 12
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#define TCE_UNUSED_SHIFT 48 /* unused */
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#define TCE_RPN_MASK 0x0000fffffffff000ULL
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extern void tce_build(struct iommu_table *tbl, unsigned long index,
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unsigned int npages, unsigned long uaddr, int direction);
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extern void tce_free(struct iommu_table *tbl, long index, unsigned int npages);
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extern void* alloc_tce_table(void);
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extern void free_tce_table(void *tbl);
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extern int build_tce_table(struct pci_dev *dev, void __iomem *bbar);
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#endif /* _ASM_X86_64_TCE_H */
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