f50b153b19
To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
42 lines
980 B
C
42 lines
980 B
C
/*
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* arch/ppc/syslib/ppc85xx_common.c
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*
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* MPC85xx support routines
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2004 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <asm/mpc85xx.h>
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#include <asm/mmu.h>
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/* ************************************************************************ */
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/* Return the value of CCSRBAR for the current board */
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phys_addr_t
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get_ccsrbar(void)
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{
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return BOARD_CCSRBAR;
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}
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EXPORT_SYMBOL(get_ccsrbar);
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/* For now this is a pass through */
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phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
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{
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return addr;
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};
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EXPORT_SYMBOL(fixup_bigphys_addr);
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