7179380ee9
Not every alchemy-based board might want these options forced on it, and most of this stuff seems to be intended for devboard code anyway. Remove commandline mangling code out of common chip code and instead add relevant sections to all in-tree boards to not change existing behaviour. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
160 lines
5.0 KiB
C
160 lines
5.0 KiB
C
/*
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-pb1x00/pb1500.h>
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#include <prom.h>
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char irq_tab_alchemy[][5] __initdata = {
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[12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
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[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
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};
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 },
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{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
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{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
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{ AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 },
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{ AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
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};
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int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
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const char *get_system_type(void)
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{
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return "Alchemy Pb1500";
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}
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void board_reset(void)
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{
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/* Hit BCSR.RST_VDDI[SOFT_RESET] */
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au_writel(0x00000000, PB1500_RST_VDDI);
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}
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void __init board_setup(void)
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{
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u32 pin_func;
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u32 sys_freqctrl, sys_clksrc;
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char *argptr;
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argptr = prom_getcmdline();
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#ifdef CONFIG_SERIAL_8250_CONSOLE
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argptr = strstr(argptr, "console=");
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if (argptr == NULL) {
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argptr = prom_getcmdline();
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strcat(argptr, " console=ttyS0,115200");
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}
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#endif
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#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
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/* au1000 does not support vra, au1500 and au1100 do */
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strcat(argptr, " au1000_audio=vra");
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argptr = prom_getcmdline();
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#endif
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sys_clksrc = sys_freqctrl = pin_func = 0;
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/* Set AUX clock to 12 MHz * 8 = 96 MHz */
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au_writel(8, SYS_AUXPLL);
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au_writel(0, SYS_PINSTATERD);
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udelay(100);
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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/* GPIO201 is input for PCMCIA card detect */
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/* GPIO203 is input for PCMCIA interrupt request */
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au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR);
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/* Zero and disable FREQ2 */
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* zero and disable USBH/USBD clocks */
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
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SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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au_writel(sys_clksrc, SYS_CLKSRC);
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
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SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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/* FREQ2 = aux/2 = 48 MHz */
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sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/*
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* Route 48MHz FREQ2 into USB Host and/or Device
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*/
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sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
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au_writel(sys_clksrc, SYS_CLKSRC);
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pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
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/* 2nd USB port is USB host */
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pin_func |= SYS_PF_USB;
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au_writel(pin_func, SYS_PINFUNC);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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#ifdef CONFIG_PCI
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/* Setup PCI bus controller */
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au_writel(0, Au1500_PCI_CMEM);
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au_writel(0x00003fff, Au1500_CFG_BASE);
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#if defined(__MIPSEB__)
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au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
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#else
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au_writel(0xf, Au1500_PCI_CFG);
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#endif
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au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
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au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
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au_writel(0x02a00356, Au1500_PCI_STATCMD);
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au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
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au_writel(0x00000008, Au1500_PCI_MBAR);
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au_sync();
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#endif
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/* Enable sys bus clock divider when IDLE state or no bus activity. */
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au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
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/* Enable the RTC if not already enabled */
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if (!(au_readl(0xac000028) & 0x20)) {
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printk(KERN_INFO "enabling clock ...\n");
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au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
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}
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/* Put the clock in BCD mode */
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if (au_readl(0xac00002c) & 0x4) { /* reg B */
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au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
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au_sync();
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}
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}
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