1cea7326b3
Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
62 lines
1.9 KiB
ArmAsm
62 lines
1.9 KiB
ArmAsm
#include <linux/linkage.h>
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#include <linux/init.h>
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.section ".text.head", "ax"
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__CPUINIT
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/*
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* Tegra specific entry point for secondary CPUs.
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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ENTRY(tegra_secondary_startup)
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msr cpsr_fsxc, #0xd3
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bl v7_invalidate_l1
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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ldr r1, =0x6000f100
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str r0, [r1]
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1: ldr r2, [r1]
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cmp r0, r2
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beq 1b
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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