5875013900
With the current kbuild infrastructure in place no other changes are required for this to work. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/****************************************************************************/
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/*
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* anchor.h -- Anchor CO-MEM Lite PCI host bridge part.
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*
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* (C) Copyright 2000, Moreton Bay (www.moreton.com.au)
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*/
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/****************************************************************************/
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#ifndef anchor_h
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#define anchor_h
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/****************************************************************************/
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/*
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* Define basic addressing info.
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*/
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#if defined(CONFIG_M5407C3)
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#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */
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#define COMEM_IRQ 25 /* IRQ of anchor part */
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#else
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#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */
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#define COMEM_IRQ 25 /* IRQ of anchor part */
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#endif
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/****************************************************************************/
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/*
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* 4-byte registers of CO-MEM, so adjust register addresses for
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* easy access. Handy macro for word access too.
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*/
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#define LREG(a) ((a) >> 2)
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#define WREG(a) ((a) >> 1)
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/*
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* Define base addresses within CO-MEM Lite register address space.
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*/
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#define COMEM_I2O 0x0000 /* I2O registers */
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#define COMEM_OPREGS 0x0400 /* Operation registers */
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#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */
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#define COMEM_SHMEM 0x4000 /* Shared memory region */
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#define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */
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/*
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* Define CO-MEM Registers.
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*/
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#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */
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#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */
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#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */
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#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */
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#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */
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#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */
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#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */
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#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */
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#define COMEM_DAHBASE 0x0460 /* Direct access base address */
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#define COMEM_NVCMD 0x04a0 /* I2C serial command */
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#define COMEM_NVREAD 0x04a4 /* I2C serial read */
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#define COMEM_NVSTAT 0x04a8 /* I2C status */
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#define COMEM_DMALBASE 0x04b0 /* DMA local base address */
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#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */
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#define COMEM_DMASIZE 0x04b8 /* DMA size */
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#define COMEM_DMACTL 0x04bc /* DMA control */
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#define COMEM_HCTL 0x04e0 /* Host control */
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#define COMEM_HINT 0x04e4 /* Host interrupt control/status */
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#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */
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#define COMEM_LINT 0x04f4 /* Local interrupt contole status */
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#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */
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#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */
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/*
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* Commands and flags for use with Direct Access Register.
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*/
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#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */
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#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */
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#define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */
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#define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */
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#define COMEM_DA_IORD 0x00000002 /* I/O read cycle */
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#define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */
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#define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */
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#define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */
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#define COMEM_DA_ADDR(a) ((a) & 0xffffe000)
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#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff)
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/*
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* The PCI bus will be limited in what slots will actually be used.
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* Define valid device numbers for different boards.
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*/
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#if defined(CONFIG_M5407C3)
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#define COMEM_MINDEV 14 /* Minimum valid DEVICE */
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#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */
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#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */
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#else
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#define COMEM_MINDEV 0 /* Minimum valid DEVICE */
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#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */
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#endif
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#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */
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/****************************************************************************/
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#endif /* anchor_h */
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