1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
363 lines
8.8 KiB
C
363 lines
8.8 KiB
C
/*
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* arch/sh/mm/cache-sh4.c
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*
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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* Copyright (C) 2001, 2002, 2003, 2004 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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extern void __flush_cache_4096_all(unsigned long start);
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static void __flush_cache_4096_all_ex(unsigned long start);
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extern void __flush_dcache_all(void);
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static void __flush_dcache_all_ex(void);
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/*
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* SH-4 has virtually indexed and physically tagged cache.
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*/
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struct semaphore p3map_sem[4];
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void __init p3_cache_init(void)
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{
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if (remap_area_pages(P3SEG, 0, PAGE_SIZE*4, _PAGE_CACHABLE))
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panic("%s failed.", __FUNCTION__);
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sema_init (&p3map_sem[0], 1);
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sema_init (&p3map_sem[1], 1);
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sema_init (&p3map_sem[2], 1);
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sema_init (&p3map_sem[3], 1);
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}
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/*
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* Write back the dirty D-caches, but not invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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void __flush_wback_region(void *start, int size)
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{
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unsigned long v;
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unsigned long begin, end;
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begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
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end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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for (v = begin; v < end; v+=L1_CACHE_BYTES) {
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asm volatile("ocbwb %0"
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: /* no output */
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: "m" (__m(v)));
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}
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}
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/*
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* Write back the dirty D-caches and invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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void __flush_purge_region(void *start, int size)
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{
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unsigned long v;
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unsigned long begin, end;
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begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
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end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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for (v = begin; v < end; v+=L1_CACHE_BYTES) {
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asm volatile("ocbp %0"
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: /* no output */
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: "m" (__m(v)));
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}
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}
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/*
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* No write back please
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*/
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void __flush_invalidate_region(void *start, int size)
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{
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unsigned long v;
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unsigned long begin, end;
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begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
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end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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for (v = begin; v < end; v+=L1_CACHE_BYTES) {
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asm volatile("ocbi %0"
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: /* no output */
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: "m" (__m(v)));
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}
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}
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static void __flush_dcache_all_ex(void)
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{
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unsigned long addr, end_addr, entry_offset;
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end_addr = CACHE_OC_ADDRESS_ARRAY + (cpu_data->dcache.sets << cpu_data->dcache.entry_shift) * cpu_data->dcache.ways;
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entry_offset = 1 << cpu_data->dcache.entry_shift;
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for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; addr += entry_offset) {
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ctrl_outl(0, addr);
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}
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}
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static void __flush_cache_4096_all_ex(unsigned long start)
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{
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unsigned long addr, entry_offset;
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int i;
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entry_offset = 1 << cpu_data->dcache.entry_shift;
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for (i = 0; i < cpu_data->dcache.ways; i++, start += cpu_data->dcache.way_incr) {
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for (addr = CACHE_OC_ADDRESS_ARRAY + start;
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addr < CACHE_OC_ADDRESS_ARRAY + 4096 + start;
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addr += entry_offset) {
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ctrl_outl(0, addr);
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}
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}
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}
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void flush_cache_4096_all(unsigned long start)
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{
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if (cpu_data->dcache.ways == 1)
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__flush_cache_4096_all(start);
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else
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__flush_cache_4096_all_ex(start);
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}
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/*
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* Write back the range of D-cache, and purge the I-cache.
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*
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* Called from kernel/module.c:sys_init_module and routine for a.out format.
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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flush_cache_all();
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}
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/*
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* Write back the D-cache and purge the I-cache for signal trampoline.
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* .. which happens to be the same behavior as flush_icache_range().
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* So, we simply flush out a line.
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*/
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void flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long v, index;
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unsigned long flags;
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int i;
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v = addr & ~(L1_CACHE_BYTES-1);
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asm volatile("ocbwb %0"
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: /* no output */
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: "m" (__m(v)));
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index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask);
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local_irq_save(flags);
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jump_to_P2();
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for(i = 0; i < cpu_data->icache.ways; i++, index += cpu_data->icache.way_incr)
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ctrl_outl(0, index); /* Clear out Valid-bit */
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back_to_P1();
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local_irq_restore(flags);
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}
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static inline void flush_cache_4096(unsigned long start,
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unsigned long phys)
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{
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unsigned long flags;
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extern void __flush_cache_4096(unsigned long addr, unsigned long phys, unsigned long exec_offset);
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/*
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* SH7751, SH7751R, and ST40 have no restriction to handle cache.
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* (While SH7750 must do that at P2 area.)
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*/
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if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG)
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|| start < CACHE_OC_ADDRESS_ARRAY) {
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local_irq_save(flags);
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__flush_cache_4096(start | SH_CACHE_ASSOC, P1SEGADDR(phys), 0x20000000);
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local_irq_restore(flags);
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} else {
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__flush_cache_4096(start | SH_CACHE_ASSOC, P1SEGADDR(phys), 0);
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}
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}
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/*
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* Write back & invalidate the D-cache of the page.
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* (To avoid "alias" issues)
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*/
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void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = PHYSADDR(page_address(page));
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/* Loop all the D-cache */
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flush_cache_4096(CACHE_OC_ADDRESS_ARRAY, phys);
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flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x1000, phys);
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flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x2000, phys);
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flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x3000, phys);
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}
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}
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static inline void flush_icache_all(void)
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{
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unsigned long flags, ccr;
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local_irq_save(flags);
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jump_to_P2();
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/* Flush I-cache */
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ccr = ctrl_inl(CCR);
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ccr |= CCR_CACHE_ICI;
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ctrl_outl(ccr, CCR);
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back_to_P1();
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local_irq_restore(flags);
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}
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void flush_cache_all(void)
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{
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if (cpu_data->dcache.ways == 1)
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__flush_dcache_all();
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else
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__flush_dcache_all_ex();
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flush_icache_all();
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}
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void flush_cache_mm(struct mm_struct *mm)
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{
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/* Is there any good way? */
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/* XXX: possibly call flush_cache_range for each vm area */
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/*
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* FIXME: Really, the optimal solution here would be able to flush out
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* individual lines created by the specified context, but this isn't
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* feasible for a number of architectures (such as MIPS, and some
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* SPARC) .. is this possible for SuperH?
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*
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* In the meantime, we'll just flush all of the caches.. this
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* seems to be the simplest way to avoid at least a few wasted
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* cache flushes. -Lethal
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*/
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flush_cache_all();
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}
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/*
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* Write back and invalidate I/D-caches for the page.
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*
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* ADDR: Virtual Address (U0 address)
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* PFN: Physical page number
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*/
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void flush_cache_page(struct vm_area_struct *vma, unsigned long address, unsigned long pfn)
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{
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unsigned long phys = pfn << PAGE_SHIFT;
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/* We only need to flush D-cache when we have alias */
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if ((address^phys) & CACHE_ALIAS) {
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/* Loop 4K of the D-cache */
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flush_cache_4096(
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CACHE_OC_ADDRESS_ARRAY | (address & CACHE_ALIAS),
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phys);
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/* Loop another 4K of the D-cache */
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flush_cache_4096(
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CACHE_OC_ADDRESS_ARRAY | (phys & CACHE_ALIAS),
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phys);
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}
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if (vma->vm_flags & VM_EXEC)
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/* Loop 4K (half) of the I-cache */
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flush_cache_4096(
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CACHE_IC_ADDRESS_ARRAY | (address & 0x1000),
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phys);
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}
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/*
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* Write back and invalidate D-caches.
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*
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* START, END: Virtual Address (U0 address)
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*
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* NOTE: We need to flush the _physical_ page entry.
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* Flushing the cache lines for U0 only isn't enough.
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* We need to flush for P1 too, which may contain aliases.
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*/
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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unsigned long p = start & PAGE_MASK;
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pgd_t *dir;
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pmd_t *pmd;
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pte_t *pte;
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pte_t entry;
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unsigned long phys;
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unsigned long d = 0;
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dir = pgd_offset(vma->vm_mm, p);
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pmd = pmd_offset(dir, p);
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do {
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if (pmd_none(*pmd) || pmd_bad(*pmd)) {
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p &= ~((1 << PMD_SHIFT) -1);
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p += (1 << PMD_SHIFT);
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pmd++;
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continue;
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}
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pte = pte_offset_kernel(pmd, p);
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do {
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entry = *pte;
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if ((pte_val(entry) & _PAGE_PRESENT)) {
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phys = pte_val(entry)&PTE_PHYS_MASK;
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if ((p^phys) & CACHE_ALIAS) {
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d |= 1 << ((p & CACHE_ALIAS)>>12);
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d |= 1 << ((phys & CACHE_ALIAS)>>12);
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if (d == 0x0f)
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goto loop_exit;
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}
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}
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pte++;
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p += PAGE_SIZE;
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} while (p < end && ((unsigned long)pte & ~PAGE_MASK));
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pmd++;
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} while (p < end);
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loop_exit:
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if (d & 1)
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flush_cache_4096_all(0);
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if (d & 2)
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flush_cache_4096_all(0x1000);
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if (d & 4)
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flush_cache_4096_all(0x2000);
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if (d & 8)
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flush_cache_4096_all(0x3000);
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if (vma->vm_flags & VM_EXEC)
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flush_icache_all();
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}
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/*
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* flush_icache_user_range
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* @vma: VMA of the process
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* @page: page
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* @addr: U0 address
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* @len: length of the range (< page size)
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*/
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void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr, int len)
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{
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flush_cache_page(vma, addr, page_to_pfn(page));
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}
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