6c0a11c118
On the 85xx/86xx PCIe controllers if there is no device connected to the PHB we will still allocate a pci_bus for downstream bus of the virtual P2P bridge. However the resources allocated to the downstream bus are not correct and so we just mimic the resources from the upstream pci_bus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
277 lines
6.6 KiB
C
277 lines
6.6 KiB
C
/*
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* MPC85xx setup and early boot code plus other random bits.
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ipic.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/i8259.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "mpc85xx.h"
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static int cds_pci_slot = 2;
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static volatile u8 *cadmus;
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#ifdef CONFIG_PCI
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#define ARCADIA_HOST_BRIDGE_IDSEL 17
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#define ARCADIA_2ND_BRIDGE_IDSEL 3
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static int mpc85xx_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn)
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{
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/* We explicitly do not go past the Tundra 320 Bridge */
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if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
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{
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u_char c;
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if (dev->vendor == PCI_VENDOR_ID_VIA) {
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switch (dev->device) {
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case PCI_DEVICE_ID_VIA_82C586_1:
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/*
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* U-Boot does not set the enable bits
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* for the IDE device. Force them on here.
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*/
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pci_read_config_byte(dev, 0x40, &c);
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c |= 0x03; /* IDE: Chip Enable Bits */
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pci_write_config_byte(dev, 0x40, c);
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/*
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* Since only primary interface works, force the
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* IDE function to standard primary IDE interrupt
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* w/ 8259 offset
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*/
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dev->irq = 14;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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break;
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/*
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* Force legacy USB interrupt routing
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*/
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case PCI_DEVICE_ID_VIA_82C586_2:
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/* There are two USB controllers.
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* Identify them by functon number
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*/
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if (PCI_FUNC(dev->devfn))
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dev->irq = 11;
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else
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dev->irq = 10;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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default:
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break;
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}
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}
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}
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#ifdef CONFIG_PPC_I8259
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#warning The i8259 PIC support is currently broken
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static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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desc->chip->eoi(irq);
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}
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#endif /* PPC_I8259 */
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#endif /* CONFIG_PCI */
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static void __init mpc85xx_cds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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#ifdef CONFIG_PPC_I8259
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struct device_node *cascade_node = NULL;
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int cascade_irq;
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#endif
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np = of_find_node_by_type(np, "open-pic");
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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/* Return the mpic node */
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of_node_put(np);
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mpic_init(mpic);
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#ifdef CONFIG_PPC_I8259
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/* Initialize the i8259 controller */
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for_each_node_by_type(np, "interrupt-controller")
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if (of_device_is_compatible(np, "chrp,iic")) {
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cascade_node = np;
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break;
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}
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if (cascade_node == NULL) {
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printk(KERN_DEBUG "Could not find i8259 PIC\n");
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return;
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}
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cascade_irq = irq_of_parse_and_map(cascade_node, 0);
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if (cascade_irq == NO_IRQ) {
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printk(KERN_ERR "Failed to map cascade interrupt\n");
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return;
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}
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i8259_init(cascade_node, 0);
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of_node_put(cascade_node);
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set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
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#endif /* CONFIG_PPC_I8259 */
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}
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/*
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* Setup the architecture
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*/
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static void __init mpc85xx_cds_setup_arch(void)
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{
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struct device_node *cpu;
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
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cpu = of_find_node_by_type(NULL, "cpu");
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if (cpu != 0) {
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const unsigned int *fp;
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fp = of_get_property(cpu, "clock-frequency", NULL);
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if (fp != 0)
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loops_per_jiffy = *fp / HZ;
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else
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loops_per_jiffy = 500000000 / HZ;
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of_node_put(cpu);
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}
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cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
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cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
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if (ppc_md.progress) {
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char buf[40];
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snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
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cadmus[CM_VER], cds_pci_slot);
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ppc_md.progress(buf, 0);
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}
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x9000)
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fsl_add_bridge(np, 0);
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else
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fsl_add_bridge(np, 1);
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}
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ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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}
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static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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uint memsize = total_memory;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc85xx_cds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxCDS");
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}
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define_machine(mpc85xx_cds) {
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.name = "MPC85xx CDS",
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.probe = mpc85xx_cds_probe,
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.setup_arch = mpc85xx_cds_setup_arch,
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.init_IRQ = mpc85xx_cds_pic_init,
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.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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};
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