89b831ef8b
MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F. This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations. The user may interface through sysfs files in order to change the threshold configuration. bank%d/error_count - reads current error count, write to clear. bank%d/interrupt_enable - set/clear interrupt enable. bank%d/threshold_limit - read/write the threshold limit. APIC vector 0xF9 in hw_irq.h. 5 software defined bank ids in mce.h. new apic.c function to setup threshold apic lvt. defaults to interrupt off, count enabled, and threshold limit max. sysfs interface created on /sys/devices/system/threshold. AK: added some ifdefs to make it compile on UP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/config.h>
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#include <linux/pm.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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extern int apic_verbosity;
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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#ifdef CONFIG_X86_LOCAL_APIC
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struct pt_regs;
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/*
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* Basic functions accessing APICs.
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*/
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static __inline void apic_write(unsigned long reg, unsigned int v)
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{
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*((volatile unsigned int *)(APIC_BASE+reg)) = v;
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}
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static __inline void apic_write_atomic(unsigned long reg, unsigned int v)
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{
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xchg((volatile unsigned int *)(APIC_BASE+reg), v);
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}
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static __inline unsigned int apic_read(unsigned long reg)
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{
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return *((volatile unsigned int *)(APIC_BASE+reg));
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}
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static __inline__ void apic_wait_icr_idle(void)
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{
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while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
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}
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#define FORCE_READ_AROUND_WRITE 0
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#define apic_read_around(x)
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#define apic_write_around(x,y) apic_write((x),(y))
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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extern int get_maxlvt (void);
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extern void clear_local_APIC (void);
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extern void connect_bsp_APIC (void);
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extern void disconnect_bsp_APIC (int virt_wire_setup);
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extern void disable_local_APIC (void);
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extern int verify_local_APIC (void);
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extern void cache_APIC_registers (void);
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extern void sync_Arb_IDs (void);
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extern void init_bsp_APIC (void);
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extern void setup_local_APIC (void);
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extern void init_apic_mappings (void);
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extern void smp_local_timer_interrupt (struct pt_regs * regs);
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extern void setup_boot_APIC_clock (void);
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extern void setup_secondary_APIC_clock (void);
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extern void setup_apic_nmi_watchdog (void);
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extern int reserve_lapic_nmi(void);
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extern void release_lapic_nmi(void);
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extern void disable_timer_nmi_watchdog(void);
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extern void enable_timer_nmi_watchdog(void);
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extern void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason);
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extern int APIC_init_uniprocessor (void);
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extern void disable_APIC_timer(void);
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extern void enable_APIC_timer(void);
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extern void clustered_apic_check(void);
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extern void nmi_watchdog_default(void);
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extern int setup_nmi_watchdog(char *);
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extern unsigned int nmi_watchdog;
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#define NMI_DEFAULT -1
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#define NMI_NONE 0
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#define NMI_IO_APIC 1
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#define NMI_LOCAL_APIC 2
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#define NMI_INVALID 3
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extern int disable_timer_pin_1;
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extern void setup_threshold_lvt(unsigned long lvt_off);
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#endif /* CONFIG_X86_LOCAL_APIC */
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extern unsigned boot_cpu_id;
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#endif /* __ASM_APIC_H */
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