71b973a42c
This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85. This also enables multi IRQ support for platforms that have multiple vectors bound to the same IRQ source. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
#ifndef __ASM_CPU_SH4_DMA_H
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#define __ASM_CPU_SH4_DMA_H
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/* SH7751/7760/7780 DMA IRQ sources */
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#ifdef CONFIG_CPU_SH4A
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#define DMAOR_INIT (DMAOR_DME)
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#define CHCR_TS_MASK 0x18
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#define CHCR_TS_SHIFT 3
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#include <cpu/dma-sh4a.h>
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#else /* CONFIG_CPU_SH4A */
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/*
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* SH7750/SH7751/SH7760
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*/
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#define DMTE0_IRQ 34
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#define DMTE4_IRQ 44
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#define DMTE6_IRQ 46
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#define DMAE0_IRQ 38
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#define DMAOR_INIT (0x8000|DMAOR_DME)
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#define SH_DMAC_BASE0 0xffa00000
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#define SH_DMAC_BASE1 0xffa00070
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/* Definitions for the SuperH DMAC */
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#define TM_BURST 0x00000080
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#define TS_8 0x00000010
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#define TS_16 0x00000020
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#define TS_32 0x00000030
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#define TS_64 0x00000000
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#define CHCR_TS_MASK 0x70
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#define CHCR_TS_SHIFT 4
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#define DMAOR_COD 0x00000008
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
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* with their respective values as they appear in the CHCR registers.
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*
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* Defaults to a 64-bit transfer size.
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*/
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enum {
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XMIT_SZ_64BIT,
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_256BIT,
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};
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/*
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* The DMA count is defined as the number of bytes to transfer.
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*/
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static unsigned int ts_shift[] __maybe_unused = {
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[XMIT_SZ_64BIT] = 3,
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_256BIT] = 5,
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};
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#endif
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#endif /* __ASM_CPU_SH4_DMA_H */
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