30dd568c91
Implement a performance counter with:
attr.type = PERF_TYPE_HARDWARE
attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS
attr.sample_period = 1
Using branch trace store (BTS) on x86 hardware, if available.
The from and to address for each branch can be sampled using:
PERF_SAMPLE_IP for the from address
PERF_SAMPLE_ADDR for the to address
[ v2: address review feedback, fix bugs ]
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
#ifndef _ASM_X86_PERF_COUNTER_H
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#define _ASM_X86_PERF_COUNTER_H
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/*
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* Performance counter hw details:
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*/
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#define X86_PMC_MAX_GENERIC 8
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#define X86_PMC_MAX_FIXED 3
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#define X86_PMC_IDX_GENERIC 0
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#define X86_PMC_IDX_FIXED 32
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#define X86_PMC_IDX_MAX 64
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
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#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
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#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
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#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
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#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
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/*
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* Includes eventsel and unit mask as well:
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*/
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#define ARCH_PERFMON_EVENT_MASK 0xffff
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
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(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
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#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
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/*
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* Intel "Architectural Performance Monitoring" CPUID
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* detection/enumeration details:
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*/
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union cpuid10_eax {
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struct {
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unsigned int version_id:8;
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unsigned int num_counters:8;
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unsigned int bit_width:8;
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unsigned int mask_length:8;
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} split;
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unsigned int full;
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};
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union cpuid10_edx {
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struct {
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unsigned int num_counters_fixed:4;
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unsigned int reserved:28;
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} split;
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unsigned int full;
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};
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/*
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* Fixed-purpose performance counters:
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*/
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/*
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* All 3 fixed-mode PMCs are configured via this single MSR:
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*/
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
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/*
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* The counts are available in three separate MSRs:
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*/
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/* Instr_Retired.Any: */
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
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#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
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/* CPU_CLK_Unhalted.Core: */
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
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#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
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/* CPU_CLK_Unhalted.Ref: */
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
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/*
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* We model BTS tracing as another fixed-mode PMC.
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*
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* We choose a value in the middle of the fixed counter range, since lower
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* values are used by actual fixed counters and higher values are used
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* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
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*/
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#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
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#ifdef CONFIG_PERF_COUNTERS
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extern void init_hw_perf_counters(void);
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extern void perf_counters_lapic_init(void);
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#define PERF_COUNTER_INDEX_OFFSET 0
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#else
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static inline void init_hw_perf_counters(void) { }
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static inline void perf_counters_lapic_init(void) { }
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#endif
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#endif /* _ASM_X86_PERF_COUNTER_H */
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