70d21cdeef
The "typename" field was obsoleted by the "name" field. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
582 lines
17 KiB
C
582 lines
17 KiB
C
/*
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* linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
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*
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* Toshiba RBTX4927 specific interrupt handlers
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* Copyright 2001-2002 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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IRQ Device
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00 RBTX4927-ISA/00
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01 RBTX4927-ISA/01 PS2/Keyboard
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02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
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03 RBTX4927-ISA/03
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04 RBTX4927-ISA/04
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05 RBTX4927-ISA/05
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06 RBTX4927-ISA/06
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07 RBTX4927-ISA/07
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08 RBTX4927-ISA/08
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09 RBTX4927-ISA/09
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10 RBTX4927-ISA/10
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11 RBTX4927-ISA/11
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12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
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13 RBTX4927-ISA/13
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14 RBTX4927-ISA/14 IDE
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15 RBTX4927-ISA/15
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16 TX4927-CP0/00 Software 0
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17 TX4927-CP0/01 Software 1
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18 TX4927-CP0/02 Cascade TX4927-CP0
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19 TX4927-CP0/03 Multiplexed -- do not use
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20 TX4927-CP0/04 Multiplexed -- do not use
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21 TX4927-CP0/05 Multiplexed -- do not use
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22 TX4927-CP0/06 Multiplexed -- do not use
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23 TX4927-CP0/07 CPU TIMER
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24 TX4927-PIC/00
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25 TX4927-PIC/01
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26 TX4927-PIC/02
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27 TX4927-PIC/03 Cascade RBTX4927-IOC
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28 TX4927-PIC/04
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29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
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30 TX4927-PIC/06
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31 TX4927-PIC/07
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32 TX4927-PIC/08 TX4927 SerialIO Channel 0
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33 TX4927-PIC/09 TX4927 SerialIO Channel 1
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34 TX4927-PIC/10
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35 TX4927-PIC/11
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36 TX4927-PIC/12
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37 TX4927-PIC/13
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38 TX4927-PIC/14
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39 TX4927-PIC/15
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40 TX4927-PIC/16 TX4927 PCI PCI-C
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41 TX4927-PIC/17
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42 TX4927-PIC/18
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43 TX4927-PIC/19
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44 TX4927-PIC/20
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45 TX4927-PIC/21
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46 TX4927-PIC/22 TX4927 PCI PCI-ERR
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47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
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48 TX4927-PIC/24
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49 TX4927-PIC/25
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50 TX4927-PIC/26
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51 TX4927-PIC/27
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52 TX4927-PIC/28
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53 TX4927-PIC/29
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54 TX4927-PIC/30
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55 TX4927-PIC/31
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56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
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57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
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58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
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59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
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60 RBTX4927-IOC/04
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61 RBTX4927-IOC/05
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62 RBTX4927-IOC/06
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63 RBTX4927-IOC/07
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NOTES:
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SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
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SouthBridge/ISA/pin=0 no pci irq used by this device
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SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
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SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
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SouthBridge/PMC/pin=0 no pci irq used by this device
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SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
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SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
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JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/timex.h>
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#include <asm/bootinfo.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/wbflush.h>
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#include <linux/bootmem.h>
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#include <linux/blkdev.h>
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#ifdef CONFIG_RTC_DS1742
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#include <linux/ds1742rtc.h>
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#endif
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#ifdef CONFIG_TOSHIBA_FPCIB0
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#include <asm/tx4927/smsc_fdc37m81x.h>
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#endif
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#include <asm/tx4927/toshiba_rbtx4927.h>
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#undef TOSHIBA_RBTX4927_IRQ_DEBUG
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#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
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#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000
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#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 )
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#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 )
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#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
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#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
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#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
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#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
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#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
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#endif
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#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
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static const u32 toshiba_rbtx4927_irq_debug_flag =
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(TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
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TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
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// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
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// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
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// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
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// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
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// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
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// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
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// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
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);
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#endif
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#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
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#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
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if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
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{ \
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char tmp[100]; \
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sprintf( tmp, str ); \
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printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
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}
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#else
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#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
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#endif
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#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
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#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
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#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
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#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
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#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
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#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
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#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
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#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
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#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
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#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
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extern int tx4927_using_backplane;
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#ifdef CONFIG_TOSHIBA_FPCIB0
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extern void enable_8259A_irq(unsigned int irq);
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extern void disable_8259A_irq(unsigned int irq);
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extern void mask_and_ack_8259A(unsigned int irq);
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#endif
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static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
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static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
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#ifdef CONFIG_TOSHIBA_FPCIB0
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static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
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static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
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static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
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#endif
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#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
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static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
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.name = TOSHIBA_RBTX4927_IOC_NAME,
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.ack = toshiba_rbtx4927_irq_ioc_disable,
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.mask = toshiba_rbtx4927_irq_ioc_disable,
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.mask_ack = toshiba_rbtx4927_irq_ioc_disable,
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.unmask = toshiba_rbtx4927_irq_ioc_enable,
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};
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#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
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#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
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#ifdef CONFIG_TOSHIBA_FPCIB0
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#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
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static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
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.name = TOSHIBA_RBTX4927_ISA_NAME,
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.ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
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.mask = toshiba_rbtx4927_irq_isa_disable,
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.mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
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.unmask = toshiba_rbtx4927_irq_isa_enable,
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};
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#endif
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u32 bit2num(u32 num)
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{
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u32 i;
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for (i = 0; i < (sizeof(num) * 8); i++) {
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if (num & (1 << i)) {
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return (i);
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}
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}
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return (0);
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}
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int toshiba_rbtx4927_irq_nested(int sw_irq)
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{
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u32 level3;
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u32 level4;
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u32 level5;
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level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
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if (level3) {
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sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
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if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
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goto RETURN;
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}
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}
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#ifdef CONFIG_TOSHIBA_FPCIB0
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{
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if (tx4927_using_backplane) {
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outb(0x0A, 0x20);
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level4 = inb(0x20) & 0xff;
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if (level4) {
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sw_irq =
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TOSHIBA_RBTX4927_IRQ_ISA_BEG +
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bit2num(level4);
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if (sw_irq !=
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TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
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goto RETURN;
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}
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}
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outb(0x0A, 0xA0);
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level5 = inb(0xA0) & 0xff;
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if (level5) {
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sw_irq =
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TOSHIBA_RBTX4927_IRQ_ISA_MID +
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bit2num(level5);
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goto RETURN;
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}
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}
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}
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#endif
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RETURN:
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return (sw_irq);
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}
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//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
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#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
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static struct irqaction toshiba_rbtx4927_irq_ioc_action =
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TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
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#ifdef CONFIG_TOSHIBA_FPCIB0
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static struct irqaction toshiba_rbtx4927_irq_isa_master =
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TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
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static struct irqaction toshiba_rbtx4927_irq_isa_slave =
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TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
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#endif
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/**********************************************************************************/
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/* Functions for ioc */
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/**********************************************************************************/
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static void __init toshiba_rbtx4927_irq_ioc_init(void)
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{
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int i;
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
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"beg=%d end=%d\n",
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TOSHIBA_RBTX4927_IRQ_IOC_BEG,
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TOSHIBA_RBTX4927_IRQ_IOC_END);
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for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
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i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
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set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
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handle_level_irq);
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setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
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&toshiba_rbtx4927_irq_ioc_action);
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}
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static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
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{
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volatile unsigned char v;
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
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"irq=%d\n", irq);
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if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
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|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
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"bad irq=%d\n", irq);
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panic("\n");
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}
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v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
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v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
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TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
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}
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static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
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{
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volatile unsigned char v;
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
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"irq=%d\n", irq);
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if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
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|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
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"bad irq=%d\n", irq);
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panic("\n");
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}
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v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
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v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
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TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
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}
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/**********************************************************************************/
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/* Functions for isa */
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/**********************************************************************************/
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#ifdef CONFIG_TOSHIBA_FPCIB0
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static void __init toshiba_rbtx4927_irq_isa_init(void)
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{
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int i;
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
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"beg=%d end=%d\n",
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|
TOSHIBA_RBTX4927_IRQ_ISA_BEG,
|
|
TOSHIBA_RBTX4927_IRQ_ISA_END);
|
|
|
|
for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
|
|
i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
|
|
set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type,
|
|
handle_level_irq);
|
|
|
|
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
|
|
&toshiba_rbtx4927_irq_isa_master);
|
|
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
|
|
&toshiba_rbtx4927_irq_isa_slave);
|
|
|
|
/* make sure we are looking at IRR (not ISR) */
|
|
outb(0x0A, 0x20);
|
|
outb(0x0A, 0xA0);
|
|
}
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_TOSHIBA_FPCIB0
|
|
static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
|
|
{
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
|
|
"irq=%d\n", irq);
|
|
|
|
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|
|
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
|
|
"bad irq=%d\n", irq);
|
|
panic("\n");
|
|
}
|
|
|
|
enable_8259A_irq(irq);
|
|
}
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_TOSHIBA_FPCIB0
|
|
static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
|
|
{
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
|
|
"irq=%d\n", irq);
|
|
|
|
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|
|
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
|
|
"bad irq=%d\n", irq);
|
|
panic("\n");
|
|
}
|
|
|
|
disable_8259A_irq(irq);
|
|
}
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_TOSHIBA_FPCIB0
|
|
static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
|
|
{
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
|
|
"irq=%d\n", irq);
|
|
|
|
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|
|
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
|
|
"bad irq=%d\n", irq);
|
|
panic("\n");
|
|
}
|
|
|
|
mask_and_ack_8259A(irq);
|
|
}
|
|
#endif
|
|
|
|
|
|
void __init arch_init_irq(void)
|
|
{
|
|
extern void tx4927_irq_init(void);
|
|
|
|
tx4927_irq_init();
|
|
toshiba_rbtx4927_irq_ioc_init();
|
|
#ifdef CONFIG_TOSHIBA_FPCIB0
|
|
{
|
|
if (tx4927_using_backplane) {
|
|
toshiba_rbtx4927_irq_isa_init();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
wbflush();
|
|
}
|
|
|
|
void toshiba_rbtx4927_irq_dump(char *key)
|
|
{
|
|
#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
|
|
{
|
|
u32 i, j = 0;
|
|
for (i = 0; i < NR_IRQS; i++) {
|
|
if (strcmp(irq_desc[i].chip->name, "none")
|
|
== 0)
|
|
continue;
|
|
|
|
if ((i >= 1)
|
|
&& (irq_desc[i - 1].chip->name ==
|
|
irq_desc[i].chip->name)) {
|
|
j++;
|
|
} else {
|
|
j = 0;
|
|
}
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK
|
|
(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
|
|
key, i, i, irq_desc[i].status,
|
|
(u32) irq_desc[i].chip,
|
|
(u32) irq_desc[i].action,
|
|
(u32) (irq_desc[i].action ? irq_desc[i].
|
|
action->handler : 0),
|
|
irq_desc[i].depth,
|
|
irq_desc[i].chip->name, j);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void toshiba_rbtx4927_irq_dump_pics(char *s)
|
|
{
|
|
u32 level0_m;
|
|
u32 level0_s;
|
|
u32 level1_m;
|
|
u32 level1_s;
|
|
u32 level2;
|
|
u32 level2_p;
|
|
u32 level2_s;
|
|
u32 level3_m;
|
|
u32 level3_s;
|
|
u32 level4_m;
|
|
u32 level4_s;
|
|
u32 level5_m;
|
|
u32 level5_s;
|
|
|
|
if (s == NULL)
|
|
s = "null";
|
|
|
|
level0_m = (read_c0_status() & 0x0000ff00) >> 8;
|
|
level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
|
|
|
|
level1_m = level0_m;
|
|
level1_s = level0_s & 0x87;
|
|
|
|
level2 = TX4927_RD(0xff1ff6a0);
|
|
level2_p = (((level2 & 0x10000)) ? 0 : 1);
|
|
level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
|
|
|
|
level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
|
|
level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
|
|
|
|
level4_m = inb(0x21);
|
|
outb(0x0A, 0x20);
|
|
level4_s = inb(0x20);
|
|
|
|
level5_m = inb(0xa1);
|
|
outb(0x0A, 0xa0);
|
|
level5_s = inb(0xa0);
|
|
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"dump_raw_pic() ");
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"cp0:m=0x%02x/s=0x%02x ", level0_m,
|
|
level0_s);
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"cp0:m=0x%02x/s=0x%02x ", level1_m,
|
|
level1_s);
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"pic:e=0x%02x/s=0x%02x ", level2_p,
|
|
level2_s);
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"ioc:m=0x%02x/s=0x%02x ", level3_m,
|
|
level3_s);
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"sbm:m=0x%02x/s=0x%02x ", level4_m,
|
|
level4_s);
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
|
|
"sbs:m=0x%02x/s=0x%02x ", level5_m,
|
|
level5_s);
|
|
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
|
|
s);
|
|
}
|