39f0fb6a34
The older simple ColdFire interrupt controller has no one-to-one mapping of interrupt numbers to bits in the interrupt mask register. Create a mapping array that each ColdFire CPU type can populate with its available interrupts and the bits that each use in the interrupt mask register. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
90 lines
3.0 KiB
C
90 lines
3.0 KiB
C
/****************************************************************************/
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/*
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* mcfintc.h -- support definitions for the simple ColdFire
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* Interrupt Controller
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*
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* (C) Copyright 2009, Greg Ungerer <gerg@uclinux.org>
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*/
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/****************************************************************************/
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#ifndef mcfintc_h
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#define mcfintc_h
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/****************************************************************************/
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/*
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* Most of the older ColdFire parts use the same simple interrupt
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* controller. This is currently used on the 5206, 5206e, 5249, 5307
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* and 5407 parts.
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*
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* The builtin peripherals are masked through dedicated bits in the
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* Interrupt Mask register (IMR) - and this is not indexed (or in any way
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* related to) the actual interrupt number they use. So knowing the IRQ
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* number doesn't explicitly map to a certain internal device for
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* interrupt control purposes.
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*/
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/*
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* Bit definitions for the ICR family of registers.
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*/
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#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
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#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
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#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
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#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
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#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
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#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
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#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
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#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
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#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
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#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
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#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
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#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
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#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
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/*
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* IMR bit position definitions. Not all ColdFire parts with this interrupt
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* controller actually support all of these interrupt sources. But the bit
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* numbers are the same in all cores.
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*/
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#define MCFINTC_EINT1 1 /* External int #1 */
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#define MCFINTC_EINT2 2 /* External int #2 */
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#define MCFINTC_EINT3 3 /* External int #3 */
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#define MCFINTC_EINT4 4 /* External int #4 */
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#define MCFINTC_EINT5 5 /* External int #5 */
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#define MCFINTC_EINT6 6 /* External int #6 */
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#define MCFINTC_EINT7 7 /* External int #7 */
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#define MCFINTC_SWT 8 /* Software Watchdog */
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#define MCFINTC_TIMER1 9
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#define MCFINTC_TIMER2 10
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#define MCFINTC_I2C 11 /* I2C / MBUS */
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#define MCFINTC_UART0 12
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#define MCFINTC_UART1 13
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#define MCFINTC_DMA0 14
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#define MCFINTC_DMA1 15
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#define MCFINTC_DMA2 16
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#define MCFINTC_DMA3 17
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#define MCFINTC_QSPI 18
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#ifndef __ASSEMBLER__
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/*
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* There is no one-is-one correspondance between the interrupt number (irq)
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* and the bit fields on the mask register. So we create a per-cpu type
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* mapping of irq to mask bit. The CPU platform code needs to register
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* its supported irq's at init time, using this function.
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*/
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extern unsigned char mcf_irq2imr[];
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static inline void mcf_mapirq2imr(int irq, int imr)
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{
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mcf_irq2imr[irq] = imr;
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}
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void mcf_autovector(int irq);
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void mcf_setimr(int index);
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void mcf_clrimr(int index);
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#endif
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/****************************************************************************/
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#endif /* mcfintc_h */
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