bc71c0961c
This adds support for the U9540 variant of the U8500 series. This is an application processor without internal modem. This is the most basic part with ASIC ID, CPU-related fixes, IRQ list, register ranges, timer, UART, and L2 cache setup. This is based on a patch by Michel Jaouen which was rewritten to fit with the latest 3.3 kernel. ChangeLog v1->v2: deleted the irqs-db9540.h file since we expect to migrate to using Device Tree for getting the IRQs to devices. ChangeLog v2->v3: introduced a fixed virtual offset for the ROM as suggested by Arnd Bergmann. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sebastien Pasdeloup <sebastien.pasdeloup-nonst@stericsson.com> Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
115 lines
2.4 KiB
C
115 lines
2.4 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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struct dbx500_asic_id dbx500_id;
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static unsigned int ux500_read_asicid(phys_addr_t addr)
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{
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phys_addr_t base = addr & ~0xfff;
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struct map_desc desc = {
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.virtual = UX500_VIRT_ROM,
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.pfn = __phys_to_pfn(base),
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.length = SZ_16K,
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.type = MT_DEVICE,
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};
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iotable_init(&desc, 1);
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/* As in devicemaps_init() */
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local_flush_tlb_all();
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flush_cache_all();
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return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
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}
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static void ux500_print_soc_info(unsigned int asicid)
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{
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unsigned int rev = dbx500_revision();
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pr_info("DB%4x ", dbx500_partnumber());
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if (rev == 0x01)
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pr_cont("Early Drop");
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else if (rev >= 0xA0)
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pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf);
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else
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pr_cont("Unknown");
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pr_cont(" [%#010x]\n", asicid);
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}
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static unsigned int partnumber(unsigned int asicid)
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{
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return (asicid >> 8) & 0xffff;
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}
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/*
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* SOC MIDR ASICID ADDRESS ASICID VALUE
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* DB8500ed 0x410fc090 0x9001FFF4 0x00850001
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* DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
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* DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
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* DB8500v2 0x412fc091 0x9001DBF4 0x008500B0
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* DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2
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* DB5500v1 0x412fc091 0x9001FFF4 0x005500A0
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* DB9540 0x413fc090 0xFFFFDBF4 0x009540xx
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*/
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void __init ux500_map_io(void)
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{
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unsigned int cpuid = read_cpuid_id();
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unsigned int asicid = 0;
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phys_addr_t addr = 0;
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switch (cpuid) {
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case 0x410fc090: /* DB8500ed */
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case 0x411fc091: /* DB8500v1 */
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addr = 0x9001FFF4;
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break;
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case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */
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asicid = ux500_read_asicid(0x9001DBF4);
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if (partnumber(asicid) == 0x8500 ||
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partnumber(asicid) == 0x8520)
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/* DB8500v2 */
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break;
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/* DB5500v1 */
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addr = 0x9001FFF4;
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break;
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case 0x413fc090: /* DB9540 */
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addr = 0xFFFFDBF4;
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break;
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}
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if (addr)
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asicid = ux500_read_asicid(addr);
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if (!asicid) {
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pr_err("Unable to identify SoC\n");
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ux500_unknown_soc();
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}
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dbx500_id.process = asicid >> 24;
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dbx500_id.partnumber = partnumber(asicid);
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dbx500_id.revision = asicid & 0xff;
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ux500_print_soc_info(asicid);
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}
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