baf22c1e7a
It was getting a little big, ugly and a primary source for merge conflicts. Also the old method was a bit too forgiving in that the workaround did default to off, so now there is an explicit #error forcing platform maintainers to think if they should enable a workaround for a particular platform. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
183 lines
6.1 KiB
C
183 lines
6.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle
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*/
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#ifndef _ASM_WAR_H
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#define _ASM_WAR_H
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#include <war.h>
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/*
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* Another R4600 erratum. Due to the lack of errata information the exact
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* technical details aren't known. I've experimentally found that disabling
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* interrupts during indexed I-cache flushes seems to be sufficient to deal
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* with the issue.
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*/
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#ifndef R4600_V1_INDEX_ICACHEOP_WAR
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#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
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#endif
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/*
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* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
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*
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* 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
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* Hit_Invalidate_D and Create_Dirty_Excl_D should only be
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* executed if there is no other dcache activity. If the dcache is
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* accessed for another instruction immeidately preceding when these
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* cache instructions are executing, it is possible that the dcache
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* tag match outputs used by these cache instructions will be
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* incorrect. These cache instructions should be preceded by at least
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* four instructions that are not any kind of load or store
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* instruction.
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*
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* This is not allowed: lw
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* nop
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* nop
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* nop
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* cache Hit_Writeback_Invalidate_D
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*
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* This is allowed: lw
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* nop
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* nop
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* nop
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* nop
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* cache Hit_Writeback_Invalidate_D
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*/
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#ifndef R4600_V1_HIT_CACHEOP_WAR
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#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
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#endif
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/*
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* Writeback and invalidate the primary cache dcache before DMA.
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*
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* R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
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* Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
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* operate correctly if the internal data cache refill buffer is empty. These
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* CACHE instructions should be separated from any potential data cache miss
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* by a load instruction to an uncached address to empty the response buffer."
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* (Revision 2.0 device errata from IDT available on http://www.idt.com/
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* in .pdf format.)
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*/
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#ifndef R4600_V2_HIT_CACHEOP_WAR
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#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
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#endif
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/*
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* When an interrupt happens on a CP0 register read instruction, CPU may
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* lock up or read corrupted values of CP0 registers after it enters
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* the exception handler.
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*
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* This workaround makes sure that we read a "safe" CP0 register as the
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* first thing in the exception handler, which breaks one of the
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* pre-conditions for this problem.
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*/
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#ifndef R5432_CP0_INTERRUPT_WAR
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#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
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#endif
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/*
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* Workaround for the Sibyte M3 errata the text of which can be found at
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*
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* http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
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*
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* This will enable the use of a special TLB refill handler which does a
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* consistency check on the information in c0_badvaddr and c0_entryhi and
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* will just return and take the exception again if the information was
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* found to be inconsistent.
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*/
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#ifndef BCM1250_M3_WAR
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#error Check setting of BCM1250_M3_WAR for your platform
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#endif
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/*
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* This is a DUART workaround related to glitches around register accesses
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*/
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#ifndef SIBYTE_1956_WAR
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#error Check setting of SIBYTE_1956_WAR for your platform
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#endif
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/*
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* Fill buffers not flushed on CACHE instructions
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*
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* Hit_Invalidate_I cacheops invalidate an icache line but the refill
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* for that line can get stale data from the fill buffer instead of
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* accessing memory if the previous icache miss was also to that line.
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*
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* Workaround: generate an icache refill from a different line
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*
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* Affects:
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* MIPS 4K RTL revision <3.0, PRID revision <4
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*/
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#ifndef MIPS4K_ICACHE_REFILL_WAR
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#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
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#endif
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/*
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* Missing implicit forced flush of evictions caused by CACHE
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* instruction
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*
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* Evictions caused by a CACHE instructions are not forced on to the
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* bus. The BIU gives higher priority to fetches than to the data from
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* the eviction buffer and no collision detection is performed between
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* fetches and pending data from the eviction buffer.
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*
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* Workaround: Execute a SYNC instruction after the cache instruction
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*
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* Affects:
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* MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
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* MIPS 20Kc RTL revision <4.0, PRID revision <?
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*/
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#ifndef MIPS_CACHE_SYNC_WAR
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#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
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#endif
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/*
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* From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
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* the line which this instruction itself exists, the following
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* operation is not guaranteed."
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*
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* Workaround: do two phase flushing for Index_Invalidate_I
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*/
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#ifndef TX49XX_ICACHE_INDEX_INV_WAR
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#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
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#endif
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/*
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* On the RM9000 there is a problem which makes the CreateDirtyExclusive
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* eache operation unusable on SMP systems.
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*/
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#ifndef RM9000_CDEX_SMP_WAR
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#error Check setting of RM9000_CDEX_SMP_WAR for your platform
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#endif
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/*
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* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
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* opposes it being called that) where invalid instructions in the same
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* I-cache line worth of instructions being fetched may case spurious
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* exceptions.
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*/
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#ifndef ICACHE_REFILLS_WORKAROUND_WAR
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#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
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#endif
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/*
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* On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
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* may cause ll / sc and lld / scd sequences to execute non-atomically.
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*/
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#ifndef R10000_LLSC_WAR
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#error Check setting of R10000_LLSC_WAR for your platform
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#endif
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/*
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* 34K core erratum: "Problems Executing the TLBR Instruction"
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*/
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#ifndef MIPS34K_MISSED_ITLB_WAR
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#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
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#endif
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#endif /* _ASM_WAR_H */
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