66d2cc95d1
Adds support for the two PCI busses on MPC83xx and the MPC834x SYS/PIBS reference board. The code initializes PCI inbound/outbound windows, allocates and registers PCI memory/io space. Be aware that setup of the PCI buses on the PIBs board is expected to be done by the firmware. Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
152 lines
3.5 KiB
C
152 lines
3.5 KiB
C
/* Created by Tony Li <tony.li@freescale.com>
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* Copyright (c) 2005 freescale semiconductor
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
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#define __PPC_SYSLIB_PPC83XX_PCI_H
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typedef struct immr_clk {
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u32 spmr; /* system PLL mode Register */
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u32 occr; /* output clock control Register */
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u32 sccr; /* system clock control Register */
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u8 res0[0xF4];
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} immr_clk_t;
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/*
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* Sequencer
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*/
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typedef struct immr_ios {
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u32 potar0;
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u8 res0[4];
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u32 pobar0;
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u8 res1[4];
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u32 pocmr0;
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u8 res2[4];
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u32 potar1;
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u8 res3[4];
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u32 pobar1;
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u8 res4[4];
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u32 pocmr1;
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u8 res5[4];
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u32 potar2;
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u8 res6[4];
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u32 pobar2;
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u8 res7[4];
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u32 pocmr2;
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u8 res8[4];
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u32 potar3;
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u8 res9[4];
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u32 pobar3;
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u8 res10[4];
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u32 pocmr3;
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u8 res11[4];
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u32 potar4;
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u8 res12[4];
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u32 pobar4;
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u8 res13[4];
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u32 pocmr4;
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u8 res14[4];
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u32 potar5;
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u8 res15[4];
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u32 pobar5;
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u8 res16[4];
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u32 pocmr5;
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u8 res17[4];
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u8 res18[0x60];
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u32 pmcr;
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u8 res19[4];
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u32 dtcr;
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u8 res20[4];
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} immr_ios_t;
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#define POTAR_TA_MASK 0x000fffff
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#define POBAR_BA_MASK 0x000fffff
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#define POCMR_EN 0x80000000
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#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
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#define POCMR_SE 0x20000000 /* streaming enable */
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#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
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#define POCMR_CM_MASK 0x000fffff
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/*
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* PCI Controller Control and Status Registers
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*/
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typedef struct immr_pcictrl {
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u32 esr;
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u32 ecdr;
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u32 eer;
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u32 eatcr;
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u32 eacr;
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u32 eeacr;
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u32 edlcr;
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u32 edhcr;
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u32 gcr;
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u32 ecr;
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u32 gsr;
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u8 res0[12];
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u32 pitar2;
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u8 res1[4];
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u32 pibar2;
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u32 piebar2;
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u32 piwar2;
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u8 res2[4];
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u32 pitar1;
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u8 res3[4];
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u32 pibar1;
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u32 piebar1;
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u32 piwar1;
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u8 res4[4];
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u32 pitar0;
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u8 res5[4];
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u32 pibar0;
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u8 res6[4];
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u32 piwar0;
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u8 res7[132];
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} immr_pcictrl_t;
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#define PITAR_TA_MASK 0x000fffff
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#define PIBAR_MASK 0xffffffff
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#define PIEBAR_EBA_MASK 0x000fffff
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#define PIWAR_EN 0x80000000
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#define PIWAR_PF 0x20000000
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#define PIWAR_RTT_MASK 0x000f0000
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#define PIWAR_RTT_NO_SNOOP 0x00040000
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#define PIWAR_RTT_SNOOP 0x00050000
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#define PIWAR_WTT_MASK 0x0000f000
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#define PIWAR_WTT_NO_SNOOP 0x00004000
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#define PIWAR_WTT_SNOOP 0x00005000
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#define PIWAR_IWS_MASK 0x0000003F
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#define PIWAR_IWS_4K 0x0000000B
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#define PIWAR_IWS_8K 0x0000000C
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#define PIWAR_IWS_16K 0x0000000D
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#define PIWAR_IWS_32K 0x0000000E
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#define PIWAR_IWS_64K 0x0000000F
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#define PIWAR_IWS_128K 0x00000010
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#define PIWAR_IWS_256K 0x00000011
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#define PIWAR_IWS_512K 0x00000012
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#define PIWAR_IWS_1M 0x00000013
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#define PIWAR_IWS_2M 0x00000014
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#define PIWAR_IWS_4M 0x00000015
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#define PIWAR_IWS_8M 0x00000016
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#define PIWAR_IWS_16M 0x00000017
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#define PIWAR_IWS_32M 0x00000018
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#define PIWAR_IWS_64M 0x00000019
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#define PIWAR_IWS_128M 0x0000001A
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#define PIWAR_IWS_256M 0x0000001B
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#define PIWAR_IWS_512M 0x0000001C
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#define PIWAR_IWS_1G 0x0000001D
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#define PIWAR_IWS_2G 0x0000001E
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#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
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