492 lines
16 KiB
C
492 lines
16 KiB
C
#ifndef _M68K_DMA_H
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#define _M68K_DMA_H 1
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//#define DMA_DEBUG 1
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#ifdef CONFIG_COLDFIRE
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/*
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* ColdFire DMA Model:
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* ColdFire DMA supports two forms of DMA: Single and Dual address. Single
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* address mode emits a source address, and expects that the device will either
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* pick up the data (DMA READ) or source data (DMA WRITE). This implies that
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* the device will place data on the correct byte(s) of the data bus, as the
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* memory transactions are always 32 bits. This implies that only 32 bit
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* devices will find single mode transfers useful. Dual address DMA mode
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* performs two cycles: source read and destination write. ColdFire will
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* align the data so that the device will always get the correct bytes, thus
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* is useful for 8 and 16 bit devices. This is the mode that is supported
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* below.
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*
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* AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
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* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
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*
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* AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
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* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
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*
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* APR/18/2002 : added proper support for MCF5272 DMA controller.
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* Arthur Shipkowski (art@videon-central.com)
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*/
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfdma.h>
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/*
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* Set number of channels of DMA on ColdFire for different implementations.
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*/
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#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
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#define MAX_M68K_DMA_CHANNELS 4
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#elif defined(CONFIG_M5272)
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#define MAX_M68K_DMA_CHANNELS 1
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#else
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#define MAX_M68K_DMA_CHANNELS 2
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#endif
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extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
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extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
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#if !defined(CONFIG_M5272)
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#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
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#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
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#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
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#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
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/* I/O to memory, 8 bits, mode */
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#define DMA_MODE_READ 0
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/* memory to I/O, 8 bits, mode */
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#define DMA_MODE_WRITE 1
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/* I/O to memory, 16 bits, mode */
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#define DMA_MODE_READ_WORD 2
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/* memory to I/O, 16 bits, mode */
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#define DMA_MODE_WRITE_WORD 3
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/* I/O to memory, 32 bits, mode */
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#define DMA_MODE_READ_LONG 4
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/* memory to I/O, 32 bits, mode */
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#define DMA_MODE_WRITE_LONG 5
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/* I/O to memory, 8 bits, single-address-mode */
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#define DMA_MODE_READ_SINGLE 8
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/* memory to I/O, 8 bits, single-address-mode */
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#define DMA_MODE_WRITE_SINGLE 9
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/* I/O to memory, 16 bits, single-address-mode */
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#define DMA_MODE_READ_WORD_SINGLE 10
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/* memory to I/O, 16 bits, single-address-mode */
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#define DMA_MODE_WRITE_WORD_SINGLE 11
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/* I/O to memory, 32 bits, single-address-mode */
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#define DMA_MODE_READ_LONG_SINGLE 12
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/* memory to I/O, 32 bits, single-address-mode */
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#define DMA_MODE_WRITE_LONG_SINGLE 13
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#else /* CONFIG_M5272 is defined */
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/* Source static-address mode */
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#define DMA_MODE_SRC_SA_BIT 0x01
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/* Two bits to select between all four modes */
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#define DMA_MODE_SSIZE_MASK 0x06
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/* Offset to shift bits in */
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#define DMA_MODE_SSIZE_OFF 0x01
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/* Destination static-address mode */
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#define DMA_MODE_DES_SA_BIT 0x10
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/* Two bits to select between all four modes */
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#define DMA_MODE_DSIZE_MASK 0x60
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/* Offset to shift bits in */
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#define DMA_MODE_DSIZE_OFF 0x05
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/* Size modifiers */
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#define DMA_MODE_SIZE_LONG 0x00
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#define DMA_MODE_SIZE_BYTE 0x01
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#define DMA_MODE_SIZE_WORD 0x02
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#define DMA_MODE_SIZE_LINE 0x03
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/*
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* Aliases to help speed quick ports; these may be suboptimal, however. They
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* do not include the SINGLE mode modifiers since the MCF5272 does not have a
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* mode where the device is in control of its addressing.
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*/
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/* I/O to memory, 8 bits, mode */
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#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
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/* memory to I/O, 8 bits, mode */
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#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
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/* I/O to memory, 16 bits, mode */
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#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
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/* memory to I/O, 16 bits, mode */
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#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
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/* I/O to memory, 32 bits, mode */
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#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
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/* memory to I/O, 32 bits, mode */
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#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
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#endif /* !defined(CONFIG_M5272) */
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#if !defined(CONFIG_M5272)
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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volatile unsigned short *dmawp;
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#ifdef DMA_DEBUG
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printk("enable_dma(dmanr=%d)\n", dmanr);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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volatile unsigned short *dmawp;
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volatile unsigned char *dmapb;
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#ifdef DMA_DEBUG
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printk("disable_dma(dmanr=%d)\n", dmanr);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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dmapb = (unsigned char *) dma_base_addr[dmanr];
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/* Turn off external requests, and stop any DMA in progress */
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dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
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dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
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}
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/*
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* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while interrupts are disabled! ---
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*
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* This is a NOP for ColdFire. Provide a stub for compatibility.
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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volatile unsigned char *dmabp;
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volatile unsigned short *dmawp;
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#ifdef DMA_DEBUG
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printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
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#endif
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dmabp = (unsigned char *) dma_base_addr[dmanr];
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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// Clear config errors
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dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
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// Set command register
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dmawp[MCFDMA_DCR] =
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MCFDMA_DCR_INT | // Enable completion irq
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MCFDMA_DCR_CS | // Force one xfer per request
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MCFDMA_DCR_AA | // Enable auto alignment
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// single-address-mode
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((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
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// sets s_rw (-> r/w) high if Memory to I/0
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((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
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// Memory to I/O or I/O to Memory
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((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
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// 32 bit, 16 bit or 8 bit transfers
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((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
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((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
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MCFDMA_DCR_SSIZE_BYTE)) |
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((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
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((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
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MCFDMA_DCR_DSIZE_BYTE));
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#ifdef DEBUG_DMA
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printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
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dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
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(int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
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#endif
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}
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/* Set transfer address for specific DMA channel */
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
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{
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volatile unsigned short *dmawp;
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volatile unsigned int *dmalp;
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#ifdef DMA_DEBUG
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printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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dmalp = (unsigned int *) dma_base_addr[dmanr];
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// Determine which address registers are used for memory/device accesses
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if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
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// Source incrementing, must be memory
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dmalp[MCFDMA_SAR] = a;
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// Set dest address, must be device
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dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
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} else {
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// Destination incrementing, must be memory
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dmalp[MCFDMA_DAR] = a;
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// Set source address, must be device
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dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
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}
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#ifdef DEBUG_DMA
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printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
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__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
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(int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
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(int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
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#endif
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}
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/*
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* Specific for Coldfire - sets device address.
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* Should be called after the mode set call, and before set DMA address.
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*/
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static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
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{
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#ifdef DMA_DEBUG
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printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
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#endif
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dma_device_address[dmanr] = a;
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}
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/*
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* NOTE 2: "count" represents _bytes_.
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*/
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static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
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{
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volatile unsigned short *dmawp;
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#ifdef DMA_DEBUG
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printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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dmawp[MCFDMA_BCR] = (unsigned short)count;
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}
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/*
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* Get DMA residue count. After a DMA transfer, this
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* should return zero. Reading this while a DMA transfer is
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* still in progress will return unpredictable results.
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* Otherwise, it returns the number of _bytes_ left to transfer.
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*/
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static __inline__ int get_dma_residue(unsigned int dmanr)
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{
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volatile unsigned short *dmawp;
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unsigned short count;
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#ifdef DMA_DEBUG
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printk("get_dma_residue(dmanr=%d)\n", dmanr);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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count = dmawp[MCFDMA_BCR];
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return((int) count);
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}
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#else /* CONFIG_M5272 is defined */
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/*
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* The MCF5272 DMA controller is very different than the controller defined above
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* in terms of register mapping. For instance, with the exception of the 16-bit
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* interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
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*
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* The big difference, however, is the lack of device-requested DMA. All modes
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* are dual address transfer, and there is no 'device' setup or direction bit.
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* You can DMA between a device and memory, between memory and memory, or even between
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* two devices directly, with any combination of incrementing and non-incrementing
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* addresses you choose. This puts a crimp in distinguishing between the 'device
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* address' set up by set_dma_device_addr.
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*
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* Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
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* which will act exactly as above in -- it will look to see if the source is set to
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* autoincrement, and if so it will make the source use the set_dma_addr value and the
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* destination the set_dma_device_addr value. Otherwise the source will be set to the
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* set_dma_device_addr value and the destination will get the set_dma_addr value.
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*
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* The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
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* and make it explicit. Depending on what you're doing, one of these two should work
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* for you, but don't mix them in the same transfer setup.
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*/
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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volatile unsigned int *dmalp;
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#ifdef DMA_DEBUG
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printk("enable_dma(dmanr=%d)\n", dmanr);
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#endif
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dmalp = (unsigned int *) dma_base_addr[dmanr];
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dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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volatile unsigned int *dmalp;
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#ifdef DMA_DEBUG
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printk("disable_dma(dmanr=%d)\n", dmanr);
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#endif
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dmalp = (unsigned int *) dma_base_addr[dmanr];
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/* Turn off external requests, and stop any DMA in progress */
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dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
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dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
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}
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/*
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* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while interrupts are disabled! ---
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*
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* This is a NOP for ColdFire. Provide a stub for compatibility.
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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volatile unsigned int *dmalp;
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volatile unsigned short *dmawp;
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#ifdef DMA_DEBUG
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printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
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#endif
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dmalp = (unsigned int *) dma_base_addr[dmanr];
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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// Clear config errors
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dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
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// Set command register
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dmalp[MCFDMA_DMR] =
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MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting
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MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data.
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MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data.
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// source static-address-mode
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((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
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// dest static-address-mode
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((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
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// burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
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(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
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(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
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dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
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#ifdef DEBUG_DMA
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printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
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dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
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(int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
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#endif
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}
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/* Set transfer address for specific DMA channel */
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
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{
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volatile unsigned int *dmalp;
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#ifdef DMA_DEBUG
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printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
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#endif
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dmalp = (unsigned int *) dma_base_addr[dmanr];
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// Determine which address registers are used for memory/device accesses
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if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
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// Source incrementing, must be memory
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dmalp[MCFDMA_DSAR] = a;
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// Set dest address, must be device
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dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
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} else {
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// Destination incrementing, must be memory
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dmalp[MCFDMA_DDAR] = a;
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// Set source address, must be device
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dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
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}
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#ifdef DEBUG_DMA
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printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
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__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
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(int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
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(int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
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#endif
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}
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/*
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* Specific for Coldfire - sets device address.
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* Should be called after the mode set call, and before set DMA address.
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*/
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static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
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{
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#ifdef DMA_DEBUG
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printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
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#endif
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|
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|
dma_device_address[dmanr] = a;
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|
}
|
|
|
|
/*
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|
* NOTE 2: "count" represents _bytes_.
|
|
*
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|
* NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
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|
*/
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|
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
|
|
{
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|
volatile unsigned int *dmalp;
|
|
|
|
#ifdef DMA_DEBUG
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|
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
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|
#endif
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
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|
dmalp[MCFDMA_DBCR] = count;
|
|
}
|
|
|
|
/*
|
|
* Get DMA residue count. After a DMA transfer, this
|
|
* should return zero. Reading this while a DMA transfer is
|
|
* still in progress will return unpredictable results.
|
|
* Otherwise, it returns the number of _bytes_ left to transfer.
|
|
*/
|
|
static __inline__ int get_dma_residue(unsigned int dmanr)
|
|
{
|
|
volatile unsigned int *dmalp;
|
|
unsigned int count;
|
|
|
|
#ifdef DMA_DEBUG
|
|
printk("get_dma_residue(dmanr=%d)\n", dmanr);
|
|
#endif
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
count = dmalp[MCFDMA_DBCR];
|
|
return(count);
|
|
}
|
|
|
|
#endif /* !defined(CONFIG_M5272) */
|
|
#endif /* CONFIG_COLDFIRE */
|
|
|
|
#define MAX_DMA_CHANNELS 8
|
|
|
|
/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
|
|
occurrence should be flagged as an error. */
|
|
/* under 2.4 it is actually needed by the new bootmem allocator */
|
|
#define MAX_DMA_ADDRESS PAGE_OFFSET
|
|
|
|
/* These are in kernel/dma.c: */
|
|
extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */
|
|
extern void free_dma(unsigned int dmanr); /* release it again */
|
|
|
|
#endif /* _M68K_DMA_H */
|