157 lines
7.0 KiB
C
157 lines
7.0 KiB
C
/****************************************************************************/
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/*
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* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
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*
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* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m528xsim_h
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#define m528xsim_h
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/****************************************************************************/
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/*
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* Define the 5280/5282 SIM register set addresses.
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*/
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#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_DCR 0x44 /* SDRAM control */
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#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
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#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
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#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
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#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
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/*
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* Derek Cheung - 6 Feb 2005
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* add I2C and QSPI register definition using Freescale's MCF5282
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*/
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/* set Port AS pin for I2C or UART */
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#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
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/* Interrupt Mask Register Register Low */
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#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
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/* Interrupt Control Register 7 */
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#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
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/*********************************************************************
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*
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* Inter-IC (I2C) Module
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*
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*********************************************************************/
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/* Read/Write access macros for general use */
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#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
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#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
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#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
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#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
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#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
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/* Bit level definitions and macros */
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#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
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#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
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#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
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#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
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#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
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#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
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#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
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#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
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#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
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#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
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#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
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#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
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#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
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#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
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#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
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/*********************************************************************
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*
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* Queued Serial Peripheral Interface (QSPI) Module
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*
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*********************************************************************/
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/* Derek - 21 Feb 2005 */
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/* change to the format used in I2C */
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/* Read/Write access macros for general use */
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#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340
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#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344
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#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348
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#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C
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#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350
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#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354
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#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354
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/* Bit level definitions and macros */
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#define MCF5282_QSPI_QMR_MSTR (0x8000)
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#define MCF5282_QSPI_QMR_DOHIE (0x4000)
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#define MCF5282_QSPI_QMR_BITS_16 (0x0000)
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#define MCF5282_QSPI_QMR_BITS_8 (0x2000)
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#define MCF5282_QSPI_QMR_BITS_9 (0x2400)
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#define MCF5282_QSPI_QMR_BITS_10 (0x2800)
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#define MCF5282_QSPI_QMR_BITS_11 (0x2C00)
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#define MCF5282_QSPI_QMR_BITS_12 (0x3000)
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#define MCF5282_QSPI_QMR_BITS_13 (0x3400)
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#define MCF5282_QSPI_QMR_BITS_14 (0x3800)
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#define MCF5282_QSPI_QMR_BITS_15 (0x3C00)
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#define MCF5282_QSPI_QMR_CPOL (0x0200)
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#define MCF5282_QSPI_QMR_CPHA (0x0100)
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#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QDLYR_SPE (0x80)
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#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
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#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QWR_HALT (0x8000)
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#define MCF5282_QSPI_QWR_WREN (0x4000)
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#define MCF5282_QSPI_QWR_WRTO (0x2000)
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#define MCF5282_QSPI_QWR_CSIV (0x1000)
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#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
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#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
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#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
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#define MCF5282_QSPI_QIR_WCEFB (0x8000)
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#define MCF5282_QSPI_QIR_ABRTB (0x4000)
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#define MCF5282_QSPI_QIR_ABRTL (0x1000)
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#define MCF5282_QSPI_QIR_WCEFE (0x0800)
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#define MCF5282_QSPI_QIR_ABRTE (0x0400)
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#define MCF5282_QSPI_QIR_SPIFE (0x0100)
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#define MCF5282_QSPI_QIR_WCEF (0x0008)
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#define MCF5282_QSPI_QIR_ABRT (0x0004)
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#define MCF5282_QSPI_QIR_SPIF (0x0001)
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#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F))
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#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00))
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#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
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#define MCF5282_QSPI_QCR_CONT (0x8000)
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#define MCF5282_QSPI_QCR_BITSE (0x4000)
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#define MCF5282_QSPI_QCR_DT (0x2000)
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#define MCF5282_QSPI_QCR_DSCK (0x1000)
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#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8)
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/****************************************************************************/
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#endif /* m528xsim_h */
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