1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
326 lines
7.4 KiB
C
326 lines
7.4 KiB
C
/* Minimal serial functions needed to send messages out the serial
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* port on SMC1.
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*/
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#include <linux/types.h>
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#include <asm/mpc8260.h>
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#include <asm/cpm2.h>
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#include <asm/immap_cpm2.h>
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uint no_print;
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extern char *params[];
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extern int nparams;
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static u_char cons_hold[128], *sgptr;
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static int cons_hold_cnt;
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/* If defined, enables serial console. The value (1 through 4)
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* should designate which SCC is used, but this isn't complete. Only
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* SCC1 is known to work at this time.
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* We're only linked if SERIAL_CPM_CONSOLE=y, so we only need to test
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* SERIAL_CPM_SCC1.
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*/
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#ifdef CONFIG_SERIAL_CPM_SCC1
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#define SCC_CONSOLE 1
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#endif
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unsigned long
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serial_init(int ignored, bd_t *bd)
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{
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#ifdef SCC_CONSOLE
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volatile scc_t *sccp;
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volatile scc_uart_t *sup;
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#else
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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#endif
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm2_map_t *ip;
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volatile iop_cpm2_t *io;
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volatile cpm_cpm2_t *cp;
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uint dpaddr, memaddr;
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ip = (cpm2_map_t *)CPM_MAP_ADDR;
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cp = &ip->im_cpm;
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io = &ip->im_ioport;
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/* Perform a reset.
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*/
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cp->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
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/* Wait for it.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG);
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#ifdef CONFIG_ADS8260
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/* Enable the RS-232 transceivers.
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*/
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*(volatile uint *)(BCSR_ADDR + 4) &=
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~(BCSR1_RS232_EN1 | BCSR1_RS232_EN2);
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#endif
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#ifdef SCC_CONSOLE
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sccp = (scc_t *)&(ip->im_scc[SCC_CONSOLE-1]);
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sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
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sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
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sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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/* Use Port D for SCC1 instead of other functions.
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*/
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io->iop_ppard |= 0x00000003;
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io->iop_psord &= ~0x00000001; /* Rx */
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io->iop_psord |= 0x00000002; /* Tx */
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io->iop_pdird &= ~0x00000001; /* Rx */
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io->iop_pdird |= 0x00000002; /* Tx */
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#else
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sp = (smc_t*)&(ip->im_smc[0]);
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*(ushort *)(&ip->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
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up = (smc_uart_t *)&ip->im_dprambase[PROFF_SMC1];
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/* Disable transmitter/receiver.
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*/
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* Use Port D for SMC1 instead of other functions.
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*/
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io->iop_ppard |= 0x00c00000;
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io->iop_pdird |= 0x00400000;
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io->iop_pdird &= ~0x00800000;
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io->iop_psord &= ~0x00c00000;
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#endif
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/* Allocate space for two buffer descriptors in the DP ram.
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* For now, this address seems OK, but it may have to
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* change with newer versions of the firmware.
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*/
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dpaddr = 0x0800;
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/* Grab a few bytes from the top of memory.
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*/
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memaddr = (bd->bi_memsize - 256) & ~15;
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rbdf = (cbd_t *)&ip->im_dprambase[dpaddr];
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rbdf->cbd_bufaddr = memaddr;
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = memaddr+128;
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tbdf->cbd_sc = 0;
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/* Set up the uart parameters in the parameter ram.
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*/
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#ifdef SCC_CONSOLE
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sup->scc_genscc.scc_rbase = dpaddr;
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sup->scc_genscc.scc_tbase = dpaddr + sizeof(cbd_t);
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/* Set up the uart parameters in the
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* parameter ram.
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*/
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sup->scc_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB;
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sup->scc_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB;
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sup->scc_genscc.scc_mrblr = 128;
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sup->scc_maxidl = 8;
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sup->scc_brkcr = 1;
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sup->scc_parec = 0;
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sup->scc_frmec = 0;
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sup->scc_nosec = 0;
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sup->scc_brkec = 0;
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sup->scc_uaddr1 = 0;
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sup->scc_uaddr2 = 0;
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sup->scc_toseq = 0;
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sup->scc_char1 = 0x8000;
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sup->scc_char2 = 0x8000;
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sup->scc_char3 = 0x8000;
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sup->scc_char4 = 0x8000;
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sup->scc_char5 = 0x8000;
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sup->scc_char6 = 0x8000;
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sup->scc_char7 = 0x8000;
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sup->scc_char8 = 0x8000;
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sup->scc_rccm = 0xc0ff;
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/* Send the CPM an initialize command.
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*/
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG);
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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sccp->scc_gsmrh = 0;
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sccp->scc_gsmrl =
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(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
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/* Disable all interrupts and clear all pending
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* events.
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*/
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sccp->scc_sccm = 0;
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sccp->scc_scce = 0xffff;
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sccp->scc_dsr = 0x7e7e;
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sccp->scc_psmr = 0x3000;
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/* Wire BRG1 to SCC1. The console driver will take care of
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* others.
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*/
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ip->im_cpmux.cmx_scr = 0;
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#else
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up->smc_rbase = dpaddr;
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up->smc_tbase = dpaddr+sizeof(cbd_t);
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up->smc_rfcr = CPMFCR_EB;
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up->smc_tfcr = CPMFCR_EB;
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up->smc_brklen = 0;
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up->smc_brkec = 0;
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up->smc_brkcr = 0;
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up->smc_mrblr = 128;
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up->smc_maxidl = 8;
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->smc_smcm = 0;
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sp->smc_smce = 0xff;
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/* Set up the baud rate generator.
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*/
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ip->im_cpmux.cmx_smr = 0;
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#endif
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/* The baud rate divisor needs to be coordinated with clk_8260().
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*/
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ip->im_brgc1 =
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(((bd->bi_brgfreq/16) / bd->bi_baudrate) << 1) |
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CPM_BRG_EN;
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/* Make the first buffer the only buffer.
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*/
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Initialize Tx/Rx parameters.
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*/
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#ifdef SCC_CONSOLE
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sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#else
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG);
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/* Enable transmitter/receiver.
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*/
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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#endif
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/* This is ignored.
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*/
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return 0;
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}
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int
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serial_readbuf(u_char *cbuf)
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{
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volatile cbd_t *rbdf;
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volatile char *buf;
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#ifdef SCC_CONSOLE
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volatile scc_uart_t *sup;
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#else
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volatile smc_uart_t *up;
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#endif
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volatile cpm2_map_t *ip;
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int i, nc;
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ip = (cpm2_map_t *)CPM_MAP_ADDR;
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#ifdef SCC_CONSOLE
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sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
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rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];
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#else
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up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]);
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rbdf = (cbd_t *)&ip->im_dprambase[up->smc_rbase];
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#endif
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/* Wait for character to show up.
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*/
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buf = (char *)rbdf->cbd_bufaddr;
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while (rbdf->cbd_sc & BD_SC_EMPTY);
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nc = rbdf->cbd_datlen;
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for (i=0; i<nc; i++)
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*cbuf++ = *buf++;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return(nc);
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}
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void
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serial_putc(void *ignored, const char c)
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{
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volatile cbd_t *tbdf;
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volatile char *buf;
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#ifdef SCC_CONSOLE
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volatile scc_uart_t *sup;
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#else
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volatile smc_uart_t *up;
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#endif
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volatile cpm2_map_t *ip;
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ip = (cpm2_map_t *)CPM_MAP_ADDR;
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#ifdef SCC_CONSOLE
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sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
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tbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_tbase];
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#else
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up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]);
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tbdf = (cbd_t *)&ip->im_dprambase[up->smc_tbase];
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#endif
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/* Wait for last character to go.
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*/
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buf = (char *)tbdf->cbd_bufaddr;
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while (tbdf->cbd_sc & BD_SC_READY);
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*buf = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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}
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char
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serial_getc(void *ignored)
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{
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char c;
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if (cons_hold_cnt <= 0) {
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cons_hold_cnt = serial_readbuf(cons_hold);
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sgptr = cons_hold;
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}
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c = *sgptr++;
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cons_hold_cnt--;
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return(c);
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}
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int
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serial_tstc(void *ignored)
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{
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volatile cbd_t *rbdf;
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#ifdef SCC_CONSOLE
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volatile scc_uart_t *sup;
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#else
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volatile smc_uart_t *up;
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#endif
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volatile cpm2_map_t *ip;
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ip = (cpm2_map_t *)CPM_MAP_ADDR;
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#ifdef SCC_CONSOLE
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sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
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rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];
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#else
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up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]);
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rbdf = (cbd_t *)&ip->im_dprambase[up->smc_rbase];
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#endif
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return(!(rbdf->cbd_sc & BD_SC_EMPTY));
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}
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