1589037f87
Some devices expect a double rate ASCLK. Add a flag to let the driver know through the s_crystal_freq call. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/*
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saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
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Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SAA7115_H_
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#define _SAA7115_H_
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/* s_routing inputs, outputs, and config */
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/* SAA7111/3/4/5 HW inputs */
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#define SAA7115_COMPOSITE0 0
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#define SAA7115_COMPOSITE1 1
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#define SAA7115_COMPOSITE2 2
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#define SAA7115_COMPOSITE3 3
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#define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
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#define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
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#define SAA7115_SVIDEO0 6
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#define SAA7115_SVIDEO1 7
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#define SAA7115_SVIDEO2 8
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#define SAA7115_SVIDEO3 9
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/* outputs */
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#define SAA7115_IPORT_ON 1
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#define SAA7115_IPORT_OFF 0
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/* SAA7111 specific outputs. */
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#define SAA7111_VBI_BYPASS 2
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#define SAA7111_FMT_YUV422 0x00
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#define SAA7111_FMT_RGB 0x40
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#define SAA7111_FMT_CCIR 0x80
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#define SAA7111_FMT_YUV411 0xc0
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/* config flags */
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/* Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit
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* controls the IDQ signal polarity which is set to 'inverted' if the bit
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* it 1 and to 'default' if it is 0. */
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#define SAA7115_IDQ_IS_DEFAULT (1 << 0)
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/* s_crystal_freq values and flags */
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/* SAA7115 v4l2_crystal_freq frequency values */
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#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
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#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
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/* SAA7115 v4l2_crystal_freq audio clock control flags */
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#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
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#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
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#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
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#define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
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#endif
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