5d9b4b19f1
If using 64-bit PTEs and 4K pages then each page table has 512 entries (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows the convention that all structures in the page table (pgd_t, pmd_t, pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require 64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs it is only possible to map 1GB of virtual address space. In order to map all 4GB of virtual address space we need to adopt a 3-level page table layout. This actually works out better for CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2 areas (which are untranslated) instead of 256. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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| .. | ||
| asm | ||
| cpu-common/cpu | ||
| cpu-sh2/cpu | ||
| cpu-sh2a/cpu | ||
| cpu-sh3/cpu | ||
| cpu-sh4/cpu | ||
| cpu-sh5/cpu | ||
| mach-common/mach | ||
| mach-dreamcast/mach | ||
| mach-ecovec24/mach | ||
| mach-kfr2r09/mach | ||
| mach-landisk/mach | ||
| mach-migor/mach | ||
| mach-se/mach | ||
| mach-sh03/mach | ||