0c8de52d76
* Don't call {piix,slc90e66}_dma_2_pio() for PIO modes in
{piix,slc90e66}_tune_chipset().
* Add PIO1 handling to {piix,slc90e66}_tune_chipset().
* Bump driver version.
v2:
* Remove PIO modes from {piix,slc90e66}_dma_2_pio(), they are no longer needed
there (Noticed by Sergei)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
249 lines
6.2 KiB
C
249 lines
6.2 KiB
C
/*
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* linux/drivers/ide/pci/slc90e66.c Version 0.15 Jul 6, 2007
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*
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* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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*
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* This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
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* but this keeps the ISA-Bridge and slots alive.
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*
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <asm/io.h>
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static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
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switch(xfer_rate) {
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case XFER_UDMA_4:
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case XFER_UDMA_3:
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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case XFER_MW_DMA_2:
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return 4;
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case XFER_MW_DMA_1:
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return 3;
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case XFER_SW_DMA_2:
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return 2;
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case XFER_MW_DMA_0:
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case XFER_SW_DMA_1:
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case XFER_SW_DMA_0:
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default:
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return 0;
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}
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}
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static void slc90e66_tune_pio (ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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int is_slave = drive->dn & 1;
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int master_port = hwif->channel ? 0x42 : 0x40;
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int slave_port = 0x44;
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unsigned long flags;
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u16 master_data;
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u8 slave_data;
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int control = 0;
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/* ISP RTC */
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static const u8 timings[][2]= {
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{ 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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spin_lock_irqsave(&ide_lock, flags);
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pci_read_config_word(dev, master_port, &master_data);
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if (pio > 1)
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control |= 1; /* Programmable timing on */
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if (drive->media == ide_disk)
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control |= 4; /* Prefetch, post write */
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if (pio > 2)
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control |= 2; /* IORDY */
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if (is_slave) {
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master_data |= 0x4000;
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master_data &= ~0x0070;
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if (pio > 1) {
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/* Set PPE, IE and TIME */
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master_data |= control << 4;
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}
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pci_read_config_byte(dev, slave_port, &slave_data);
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slave_data &= hwif->channel ? 0x0f : 0xf0;
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
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(hwif->channel ? 4 : 0);
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} else {
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master_data &= ~0x3307;
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if (pio > 1) {
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/* enable PPE, IE and TIME */
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master_data |= control;
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}
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master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
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}
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pci_write_config_word(dev, master_port, master_data);
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if (is_slave)
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pci_write_config_byte(dev, slave_port, slave_data);
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spin_unlock_irqrestore(&ide_lock, flags);
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}
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static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
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{
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pio = ide_get_best_pio_mode(drive, pio, 4);
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slc90e66_tune_pio(drive, pio);
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(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
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}
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static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 maslave = hwif->channel ? 0x42 : 0x40;
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u8 speed = ide_rate_filter(drive, xferspeed);
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int sitre = 0, a_speed = 7 << (drive->dn * 4);
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int u_speed = 0, u_flag = 1 << drive->dn;
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u16 reg4042, reg44, reg48, reg4a;
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pci_read_config_word(dev, maslave, ®4042);
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sitre = (reg4042 & 0x4000) ? 1 : 0;
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pci_read_config_word(dev, 0x44, ®44);
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pci_read_config_word(dev, 0x48, ®48);
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pci_read_config_word(dev, 0x4a, ®4a);
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switch(speed) {
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case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
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case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
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case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
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case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
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case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_SW_DMA_2: break;
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0: break;
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default: return -1;
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}
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if (speed >= XFER_UDMA_0) {
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if (!(reg48 & u_flag))
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pci_write_config_word(dev, 0x48, reg48|u_flag);
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/* FIXME: (reg4a & a_speed) ? */
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if ((reg4a & u_speed) != u_speed) {
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pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
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pci_read_config_word(dev, 0x4a, ®4a);
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pci_write_config_word(dev, 0x4a, reg4a|u_speed);
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}
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} else {
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if (reg48 & u_flag)
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pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
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if (reg4a & a_speed)
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pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
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}
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if (speed > XFER_PIO_4)
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slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
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else
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slc90e66_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
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{
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drive->init_speed = 0;
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if (ide_tune_dma(drive))
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return 0;
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if (ide_use_fast_pio(drive))
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slc90e66_tune_drive(drive, 255);
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return -1;
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}
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static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
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{
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u8 reg47 = 0;
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u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
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hwif->autodma = 0;
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if (!hwif->irq)
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hwif->irq = hwif->channel ? 15 : 14;
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hwif->speedproc = &slc90e66_tune_chipset;
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hwif->tuneproc = &slc90e66_tune_drive;
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pci_read_config_byte(hwif->pci_dev, 0x47, ®47);
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if (!hwif->dma_base) {
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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return;
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}
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hwif->atapi_dma = 1;
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hwif->ultra_mask = 0x1f;
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hwif->mwdma_mask = 0x06;
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hwif->swdma_mask = 0x04;
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if (hwif->cbl != ATA_CBL_PATA40_SHORT)
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/* bit[0(1)]: 0:80, 1:40 */
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hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
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hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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static ide_pci_device_t slc90e66_chipset __devinitdata = {
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.name = "SLC90E66",
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.init_hwif = init_hwif_slc90e66,
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.autodma = AUTODMA,
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.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
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.bootable = ON_BOARD,
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.pio_mask = ATA_PIO4,
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};
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static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &slc90e66_chipset);
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}
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static struct pci_device_id slc90e66_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
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static struct pci_driver driver = {
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.name = "SLC90e66_IDE",
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.id_table = slc90e66_pci_tbl,
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.probe = slc90e66_init_one,
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};
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static int __init slc90e66_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(slc90e66_ide_init);
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MODULE_AUTHOR("Andre Hedrick");
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MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
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MODULE_LICENSE("GPL");
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