58772cd344
The clk_p83 clock, which is the PCLK clock for DSYS domain, is of type 'struct clk' whereas on S5PV210, this clock is suitable to be of type clksrc_clk clock (since it has a clock divider). So this patch replaces the 'struct clk' type clock to 'struct clksrc_clk' type clock for the PCLK DSYS clock. This patch modifies the following. 1. Remove definitions and usage of 'clk_p83' clock. 2. Adds 'clk_pclk_dsys' clock which is of type 'struct clksrc_clk'. 3. Replace all usage of clk_p83 with clk_pclk_dsys clock. 4. Adds clk_pclk_dsys into list of clocks to be registered. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
509 lines
11 KiB
C
509 lines
11 KiB
C
/* linux/arch/arm/mach-s5pv210/clock.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/cpu-freq.h>
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#include <mach/regs-clock.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/s5pv210.h>
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
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};
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
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};
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static struct clk *clkset_armclk_list[] = {
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[0] = &clk_mout_apll.clk,
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[1] = &clk_mout_mpll.clk,
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};
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static struct clksrc_sources clkset_armclk = {
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.sources = clkset_armclk_list,
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.nr_sources = ARRAY_SIZE(clkset_armclk_list),
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};
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static struct clksrc_clk clk_armclk = {
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.clk = {
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.name = "armclk",
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.id = -1,
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},
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.sources = &clkset_armclk,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_hclk_msys = {
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.clk = {
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.name = "hclk_msys",
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.id = -1,
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.parent = &clk_armclk.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
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};
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static struct clksrc_clk clk_pclk_msys = {
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.clk = {
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.name = "pclk_msys",
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.id = -1,
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.parent = &clk_hclk_msys.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
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};
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static struct clksrc_clk clk_sclk_a2m = {
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.clk = {
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.name = "sclk_a2m",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
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};
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static struct clk *clkset_hclk_sys_list[] = {
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[0] = &clk_mout_mpll.clk,
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[1] = &clk_sclk_a2m.clk,
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};
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static struct clksrc_sources clkset_hclk_sys = {
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.sources = clkset_hclk_sys_list,
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.nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
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};
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static struct clksrc_clk clk_hclk_dsys = {
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.clk = {
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.name = "hclk_dsys",
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.id = -1,
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},
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.sources = &clkset_hclk_sys,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_pclk_dsys = {
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.clk = {
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.name = "pclk_dsys",
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.id = -1,
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.parent = &clk_hclk_dsys.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
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};
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static struct clksrc_clk clk_hclk_psys = {
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.clk = {
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.name = "hclk_psys",
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.id = -1,
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},
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.sources = &clkset_hclk_sys,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
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};
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static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
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}
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static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
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}
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static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
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}
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static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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static struct clk clk_p66 = {
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.name = "pclk66",
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.id = -1,
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};
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static struct clk *sys_clks[] = {
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&clk_p66
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};
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static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / 2;
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}
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static struct clk_ops clk_hclk_imem_ops = {
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.get_rate = s5pv210_clk_imem_get_rate,
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};
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static struct clk init_clocks_disable[] = {
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{
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.name = "rot",
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.id = -1,
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.parent = &clk_hclk_dsys.clk,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1<<29),
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}, {
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.name = "otg",
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.id = -1,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<17),
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}, {
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.name = "lcd",
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.id = -1,
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.parent = &clk_hclk_dsys.clk,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<0),
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}, {
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.name = "cfcon",
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.id = 0,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<25),
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<17),
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<18),
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}, {
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.name = "hsmmc",
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.id = 3,
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.parent = &clk_hclk_psys.clk,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<19),
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}, {
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.name = "systimer",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<22),
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<15),
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}, {
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.name = "i2c",
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.id = 0,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<7),
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}, {
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.name = "i2c",
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.id = 1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<8),
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}, {
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.name = "i2c",
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.id = 2,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<9),
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<12),
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<13),
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}, {
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.name = "spi",
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.id = 2,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<14),
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<23),
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<24),
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}, {
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.name = "keypad",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<21),
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}, {
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.name = "i2s_v50",
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.id = 0,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}, {
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.name = "i2s_v32",
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.id = 0,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}, {
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.name = "i2s_v32",
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.id = 1,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "hclk_imem",
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.id = -1,
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.parent = &clk_hclk_msys.clk,
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.ctrlbit = (1 << 5),
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.enable = s5pv210_clk_ip0_ctrl,
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.ops = &clk_hclk_imem_ops,
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<7),
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<8),
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<9),
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}, {
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.name = "uart",
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.id = 3,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<10),
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},
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};
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static struct clk *clkset_uart_list[] = {
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[6] = &clk_mout_mpll.clk,
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[7] = &clk_mout_epll.clk,
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};
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static struct clksrc_sources clkset_uart = {
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.sources = clkset_uart_list,
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.nr_sources = ARRAY_SIZE(clkset_uart_list),
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "uclk1",
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.id = -1,
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.ctrlbit = (1<<17),
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.enable = s5pv210_clk_ip3_ctrl,
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
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}
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};
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/* Clock initialisation code */
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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&clk_mout_epll,
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&clk_mout_mpll,
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&clk_armclk,
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&clk_hclk_msys,
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&clk_sclk_a2m,
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&clk_hclk_dsys,
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&clk_hclk_psys,
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&clk_pclk_msys,
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&clk_pclk_dsys,
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};
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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void __init_or_cpufreq s5pv210_setup_clocks(void)
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{
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struct clk *xtal_clk;
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unsigned long xtal;
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unsigned long armclk;
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unsigned long hclk_msys;
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unsigned long hclk_dsys;
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unsigned long hclk_psys;
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unsigned long pclk_msys;
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unsigned long pclk_dsys;
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unsigned long pclk66;
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unsigned long apll;
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unsigned long mpll;
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unsigned long epll;
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unsigned int ptr;
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u32 clkdiv0, clkdiv1;
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printk(KERN_DEBUG "%s: registering clocks\n", __func__);
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clkdiv0 = __raw_readl(S5P_CLK_DIV0);
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clkdiv1 = __raw_readl(S5P_CLK_DIV1);
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printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
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__func__, clkdiv0, clkdiv1);
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xtal_clk = clk_get(NULL, "xtal");
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BUG_ON(IS_ERR(xtal_clk));
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
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apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
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apll, mpll, epll);
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armclk = clk_get_rate(&clk_armclk.clk);
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hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
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hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
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hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
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pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
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pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
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pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
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printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
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"HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
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armclk, hclk_msys, hclk_dsys, hclk_psys,
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pclk_msys, pclk_dsys, pclk66);
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clk_f.rate = armclk;
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clk_h.rate = hclk_psys;
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clk_p.rate = pclk66;
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clk_p66.rate = pclk66;
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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|
}
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
};
|
|
|
|
void __init s5pv210_register_clocks(void)
|
|
{
|
|
struct clk *clkp;
|
|
int ret;
|
|
int ptr;
|
|
|
|
ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
|
if (ret > 0)
|
|
printk(KERN_ERR "Failed to register %u clocks\n", ret);
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
|
s3c_register_clksrc(sysclks[ptr], 1);
|
|
|
|
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
|
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
|
|
|
ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
|
|
if (ret > 0)
|
|
printk(KERN_ERR "Failed to register system clocks\n");
|
|
|
|
clkp = init_clocks_disable;
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
(clkp->enable)(clkp, 0);
|
|
}
|
|
|
|
s3c_pwmclk_init();
|
|
}
|