f706bed114
The Freescale serial port's are pretty much a 16550, however there are some FSL specific bugs and features. Add a "fsl,ns16550" compatiable string to allow code to handle those FSL specific issues. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
639 lines
14 KiB
Plaintext
639 lines
14 KiB
Plaintext
/*
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* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
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* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
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*
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* XPedite5370 3U VPX single-board computer based on MPC8572E
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/ {
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model = "xes,xpedite5370";
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compatible = "xes,xpedite5370", "xes,MPC8572";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8572@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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PowerPC,8572@1 {
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device_type = "cpu";
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reg = <0x1>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
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};
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localbus@ef005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
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reg = <0 0xef005000 0 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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/* Local bus region mappings */
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ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
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1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
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2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
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3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
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nor-boot@0,0 {
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compatible = "amd,s29gl01gp", "cfi-flash";
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bank-width = <2>;
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reg = <0 0 0x8000000>; /* 128MB */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Primary user space";
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reg = <0x00000000 0x6f00000>; /* 111 MB */
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};
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partition@6f00000 {
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label = "Primary kernel";
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reg = <0x6f00000 0x1000000>; /* 16 MB */
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};
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partition@7f00000 {
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label = "Primary DTB";
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reg = <0x7f00000 0x40000>; /* 256 KB */
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};
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partition@7f40000 {
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label = "Primary U-Boot environment";
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reg = <0x7f40000 0x40000>; /* 256 KB */
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};
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partition@7f80000 {
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label = "Primary U-Boot";
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reg = <0x7f80000 0x80000>; /* 512 KB */
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read-only;
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};
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};
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nor-alternate@1,0 {
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compatible = "amd,s29gl01gp", "cfi-flash";
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bank-width = <2>;
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//reg = <0xf0000000 0x08000000>; /* 128MB */
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reg = <1 0 0x8000000>; /* 128MB */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Secondary user space";
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reg = <0x00000000 0x6f00000>; /* 111 MB */
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};
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partition@6f00000 {
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label = "Secondary kernel";
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reg = <0x6f00000 0x1000000>; /* 16 MB */
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};
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partition@7f00000 {
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label = "Secondary DTB";
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reg = <0x7f00000 0x40000>; /* 256 KB */
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};
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partition@7f40000 {
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label = "Secondary U-Boot environment";
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reg = <0x7f40000 0x40000>; /* 256 KB */
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};
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partition@7f80000 {
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label = "Secondary U-Boot";
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reg = <0x7f80000 0x80000>; /* 512 KB */
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read-only;
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};
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Actual part could be ST Micro NAND08GW3B2A (1 GB),
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* Micron MT29F8G08DAA (2x 512 MB), or Micron
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* MT29F16G08FAA (2x 1 GB), depending on the build
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* configuration
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*/
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <2 0 0x40000>;
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/* U-Boot should fix this up if chip size > 1 GB */
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partition@0 {
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label = "NAND Filesystem";
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reg = <0 0x40000000>;
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};
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};
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};
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soc8572@ef000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8572-immr", "simple-bus";
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ranges = <0x0 0 0xef000000 0x100000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8572-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8572-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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memory-controller@6000 {
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compatible = "fsl,mpc8572-memory-controller";
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reg = <0x6000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8572-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x100000>; // L2, 1M
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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temp-sensor@48 {
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compatible = "dallas,ds1631", "dallas,ds1621";
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reg = <0x48>;
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};
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temp-sensor@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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cpu-supervisor@51 {
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compatible = "dallas,ds4510";
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reg = <0x51>;
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};
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eeprom@54 {
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compatible = "atmel,at24c128b";
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reg = <0x54>;
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};
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rtc@68 {
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compatible = "stm,m41t00",
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"dallas,ds1338";
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reg = <0x68>;
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};
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pcie-switch@70 {
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compatible = "plx,pex8518";
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reg = <0x70>;
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};
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gpio1: gpio@18 {
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compatible = "nxp,pca9557";
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reg = <0x18>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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gpio2: gpio@1c {
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compatible = "nxp,pca9557";
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reg = <0x1c>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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gpio3: gpio@1e {
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compatible = "nxp,pca9557";
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reg = <0x1e>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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gpio4: gpio@1f {
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compatible = "nxp,pca9557";
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reg = <0x1f>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
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reg = <0xc300 0x4>;
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ranges = <0x0 0xc100 0x200>;
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cell-index = <1>;
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dma-channel@0 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <76 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <77 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <78 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <79 2>;
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};
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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/* eTSEC 1 */
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "sgmii";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <0x2>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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/* eTSEC 2 */
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "sgmii";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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/* UART0 */
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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/* UART1 */
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8572-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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msi@41600 {
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compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2 58 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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gpio0: gpio@f000 {
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compatible = "fsl,mpc8572-gpio";
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reg = <0xf000 0x1000>;
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interrupts = <47 2>;
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interrupt-parent = <&mpic>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio-leds {
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compatible = "gpio-leds";
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heartbeat {
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label = "Heartbeat";
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gpios = <&gpio0 4 1>;
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linux,default-trigger = "heartbeat";
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};
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yellow {
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label = "Yellow";
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gpios = <&gpio0 5 1>;
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};
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red {
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label = "Red";
|
|
gpios = <&gpio0 6 1>;
|
|
};
|
|
|
|
green {
|
|
label = "Green";
|
|
gpios = <&gpio0 7 1>;
|
|
};
|
|
};
|
|
|
|
/* PME (pattern-matcher) */
|
|
pme@10000 {
|
|
compatible = "fsl,mpc8572-pme", "pme8572";
|
|
reg = <0x10000 0x5000>;
|
|
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
tlu@2f000 {
|
|
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
|
reg = <0x2f000 0x1000>;
|
|
interupts = <61 2 >;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
tlu@15000 {
|
|
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
|
reg = <0x15000 0x1000>;
|
|
interupts = <75 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
};
|
|
|
|
/*
|
|
* PCI Express controller 3 @ ef008000 is not used.
|
|
* This would have been pci0 on other mpc85xx platforms.
|
|
*/
|
|
|
|
/* PCI Express controller 2, wired to VPX P1,P2 backplane */
|
|
pci1: pcie@ef009000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xef009000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
|
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <25 2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
|
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
|
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
|
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xc0000000
|
|
0x2000000 0x0 0xc0000000
|
|
0x0 0x10000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
|
|
/* PCI Express controller 1, wired to PEX8518 PCIe switch */
|
|
pci2: pcie@ef00a000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xef00a000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
|
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <26 2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
|
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
|
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
|
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0x80000000
|
|
0x2000000 0x0 0x80000000
|
|
0x0 0x40000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
};
|