1d015cf02a
This patch reworks the sh3/sh4/sh4a register saving code in the following ways: - break out prepare_stack_save_dsp() from handle_exception() - break out save_regs() from handle_exception() - the register saving order is unchanged - align new functions to fit in cache lines - separate exception code from interrupt code - keep main code flow in a single cache line per exception vector - use bsr/rts for regular functions (save pr first) - keep data in one shared cache line (exception_data) - document the functions - tie in the hp6xx code Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
44 lines
739 B
ArmAsm
44 lines
739 B
ArmAsm
/*
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* Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/linkage.h>
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#include <cpu/mmu_context.h>
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/*
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* Kernel mode register usage:
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* k0 scratch
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* k1 scratch
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* For more details, please have a look at entry.S
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*/
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#define k0 r0
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#define k1 r1
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ENTRY(wakeup_start)
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! clear STBY bit
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mov #-126, k1
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and #127, k0
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mov.b k0, @k1
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! enable refresh
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mov.l 5f, k1
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mov.w 6f, k0
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mov.w k0, @k1
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! jump to handler
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mov.l 4f, k1
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jmp @k1
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nop
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.align 2
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4: .long handle_interrupt
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5: .long 0xffffff68
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6: .word 0x0524
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ENTRY(wakeup_end)
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nop
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