92c548cd35
The ezLCD+101 board (to which an favr-32 is fitted) has a long, unshielded, nasty lead between the touch panel and the ads7843 touch controller. In order to get satisfactory response then, we need to employ every noise-reduction trick in the driver's arsenal. After extensive fiddling I've found some good settings: 1) We keep vref on all the time to dramatically reduce settling times (at the cost of a tiny increase in power consumption). 2) Despite 1 the settling time is still non-zero. 500uS is plenty of time for the signals to settle 3) Despite 1 and 2 there's still a little bit of noise around. By setting a pen recheck delay we make the panel feel less touchy and twitchy. Someone with more time and patience myself might be able to tune this numbers further but these settings are now perfectly acceptable for normal use. Tested on ezLCD+101 though should only improve response on other ezLCD+/ favr-32 boards too. Signed-off-by: Ben Nizette <bn@niasdigital.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
353 lines
7.8 KiB
C
353 lines
7.8 KiB
C
/*
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* Favr-32 board-specific setup code.
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/etherdevice.h>
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#include <linux/bootmem.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/linkage.h>
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#include <linux/gpio.h>
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#include <linux/leds.h>
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#include <linux/atmel-mci.h>
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#include <linux/atmel-pwm-bl.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/ads7846.h>
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#include <sound/atmel-abdac.h>
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#include <video/atmel_lcdc.h>
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#include <asm/setup.h>
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#include <mach/at32ap700x.h>
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#include <mach/init.h>
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#include <mach/board.h>
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#include <mach/portmux.h>
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/* Oscillator frequencies. These are board-specific */
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unsigned long at32_board_osc_rates[3] = {
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[0] = 32768, /* 32.768 kHz on RTC osc */
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[1] = 20000000, /* 20 MHz on osc0 */
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[2] = 12000000, /* 12 MHz on osc1 */
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};
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/* Initialized by bootloader-specific startup code. */
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struct tag *bootloader_tags __initdata;
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static struct atmel_abdac_pdata __initdata abdac0_data = {
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};
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struct eth_addr {
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u8 addr[6];
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};
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static struct eth_addr __initdata hw_addr[1];
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static struct eth_platform_data __initdata eth_data[1] = {
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{
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.phy_mask = ~(1U << 1),
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},
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};
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static int ads7843_get_pendown_state(void)
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{
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return !gpio_get_value(GPIO_PIN_PB(3));
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}
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static struct ads7846_platform_data ads7843_data = {
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.model = 7843,
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.get_pendown_state = ads7843_get_pendown_state,
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.pressure_max = 255,
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/*
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* Values below are for debounce filtering, these can be experimented
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* with further.
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*/
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.debounce_max = 20,
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.debounce_rep = 4,
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.debounce_tol = 5,
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.keep_vref_on = true,
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.settle_delay_usecs = 500,
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.penirq_recheck_delay_usecs = 100,
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};
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static struct spi_board_info __initdata spi1_board_info[] = {
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{
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/* ADS7843 touch controller */
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.modalias = "ads7846",
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.max_speed_hz = 2000000,
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.chip_select = 0,
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.bus_num = 1,
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.platform_data = &ads7843_data,
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},
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};
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static struct mci_platform_data __initdata mci0_data = {
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.slot[0] = {
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.bus_width = 4,
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.detect_pin = -ENODEV,
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.wp_pin = -ENODEV,
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},
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};
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static struct fb_videomode __initdata lb104v03_modes[] = {
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{
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.name = "640x480 @ 50",
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.refresh = 50,
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.xres = 640, .yres = 480,
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.pixclock = KHZ2PICOS(25100),
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.left_margin = 90, .right_margin = 70,
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.upper_margin = 30, .lower_margin = 15,
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.hsync_len = 12, .vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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};
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static struct fb_monspecs __initdata favr32_default_monspecs = {
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.manufacturer = "LG",
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.monitor = "LB104V03",
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.modedb = lb104v03_modes,
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.modedb_len = ARRAY_SIZE(lb104v03_modes),
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.hfmin = 27273,
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.hfmax = 31111,
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.vfmin = 45,
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.vfmax = 60,
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.dclkmax = 28000000,
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};
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struct atmel_lcdfb_info __initdata favr32_lcdc_data = {
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.default_bpp = 16,
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.default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
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.default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT
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| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
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| ATMEL_LCDC_MEMOR_BIG),
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.default_monspecs = &favr32_default_monspecs,
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.guard_time = 2,
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};
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static struct gpio_led favr32_leds[] = {
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{
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.name = "green",
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.gpio = GPIO_PIN_PE(19),
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.default_trigger = "heartbeat",
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.active_low = 1,
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},
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{
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.name = "red",
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.gpio = GPIO_PIN_PE(20),
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.active_low = 1,
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},
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};
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static struct gpio_led_platform_data favr32_led_data = {
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.num_leds = ARRAY_SIZE(favr32_leds),
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.leds = favr32_leds,
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};
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static struct platform_device favr32_led_dev = {
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.name = "leds-gpio",
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.id = 0,
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.dev = {
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.platform_data = &favr32_led_data,
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},
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};
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/*
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* The next two functions should go away as the boot loader is
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* supposed to initialize the macb address registers with a valid
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* ethernet address. But we need to keep it around for a while until
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* we can be reasonably sure the boot loader does this.
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*
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* The phy_id is ignored as the driver will probe for it.
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*/
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static int __init parse_tag_ethernet(struct tag *tag)
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{
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int i;
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i = tag->u.ethernet.mac_index;
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if (i < ARRAY_SIZE(hw_addr))
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memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
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sizeof(hw_addr[i].addr));
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return 0;
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}
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__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
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static void __init set_hw_addr(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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const u8 *addr;
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void __iomem *regs;
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struct clk *pclk;
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if (!res)
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return;
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if (pdev->id >= ARRAY_SIZE(hw_addr))
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return;
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addr = hw_addr[pdev->id].addr;
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if (!is_valid_ether_addr(addr))
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return;
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/*
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* Since this is board-specific code, we'll cheat and use the
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* physical address directly as we happen to know that it's
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* the same as the virtual address.
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*/
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regs = (void __iomem __force *)res->start;
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pclk = clk_get(&pdev->dev, "pclk");
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if (!pclk)
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return;
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clk_enable(pclk);
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__raw_writel((addr[3] << 24) | (addr[2] << 16)
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| (addr[1] << 8) | addr[0], regs + 0x98);
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__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
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clk_disable(pclk);
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clk_put(pclk);
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}
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void __init favr32_setup_leds(void)
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{
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unsigned i;
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for (i = 0; i < ARRAY_SIZE(favr32_leds); i++)
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at32_select_gpio(favr32_leds[i].gpio, AT32_GPIOF_OUTPUT);
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platform_device_register(&favr32_led_dev);
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}
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static struct atmel_pwm_bl_platform_data atmel_pwm_bl_pdata = {
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.pwm_channel = 2,
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.pwm_frequency = 200000,
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.pwm_compare_max = 345,
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.pwm_duty_max = 345,
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.pwm_duty_min = 90,
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.pwm_active_low = 1,
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.gpio_on = GPIO_PIN_PA(28),
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.on_active_low = 0,
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};
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static struct platform_device atmel_pwm_bl_dev = {
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.name = "atmel-pwm-bl",
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.id = 0,
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.dev = {
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.platform_data = &atmel_pwm_bl_pdata,
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},
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};
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static void __init favr32_setup_atmel_pwm_bl(void)
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{
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platform_device_register(&atmel_pwm_bl_dev);
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at32_select_gpio(atmel_pwm_bl_pdata.gpio_on, 0);
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}
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void __init setup_board(void)
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{
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at32_map_usart(3, 0, 0); /* USART 3 => /dev/ttyS0 */
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at32_setup_serial_console(0);
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}
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static int __init set_abdac_rate(struct platform_device *pdev)
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{
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int retval;
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struct clk *osc1;
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struct clk *pll1;
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struct clk *abdac;
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if (pdev == NULL)
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return -ENXIO;
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osc1 = clk_get(NULL, "osc1");
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if (IS_ERR(osc1)) {
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retval = PTR_ERR(osc1);
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goto out;
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}
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pll1 = clk_get(NULL, "pll1");
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if (IS_ERR(pll1)) {
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retval = PTR_ERR(pll1);
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goto out_osc1;
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}
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abdac = clk_get(&pdev->dev, "sample_clk");
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if (IS_ERR(abdac)) {
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retval = PTR_ERR(abdac);
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goto out_pll1;
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}
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retval = clk_set_parent(pll1, osc1);
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if (retval != 0)
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goto out_abdac;
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/*
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* Rate is 32000 to 50000 and ABDAC oversamples 256x. Multiply, in
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* power of 2, to a value above 80 MHz. Power of 2 so it is possible
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* for the generic clock to divide it down again and 80 MHz is the
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* lowest frequency for the PLL.
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*/
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retval = clk_round_rate(pll1,
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CONFIG_BOARD_FAVR32_ABDAC_RATE * 256 * 16);
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if (retval < 0)
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goto out_abdac;
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retval = clk_set_rate(pll1, retval);
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if (retval != 0)
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goto out_abdac;
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retval = clk_set_parent(abdac, pll1);
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if (retval != 0)
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goto out_abdac;
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out_abdac:
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clk_put(abdac);
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out_pll1:
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clk_put(pll1);
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out_osc1:
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clk_put(osc1);
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out:
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return retval;
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}
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static int __init favr32_init(void)
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{
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/*
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* Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific
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* pins so that nobody messes with them.
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*/
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at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
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at32_select_gpio(GPIO_PIN_PB(3), 0); /* IRQ from ADS7843 */
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at32_add_device_usart(0);
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set_hw_addr(at32_add_device_eth(0, ð_data[0]));
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spi1_board_info[0].irq = gpio_to_irq(GPIO_PIN_PB(3));
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set_abdac_rate(at32_add_device_abdac(0, &abdac0_data));
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at32_add_device_pwm(1 << atmel_pwm_bl_pdata.pwm_channel);
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at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
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at32_add_device_mci(0, &mci0_data);
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at32_add_device_usba(0, NULL);
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at32_add_device_lcdc(0, &favr32_lcdc_data, fbmem_start, fbmem_size, 0);
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favr32_setup_leds();
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favr32_setup_atmel_pwm_bl();
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return 0;
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}
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postcore_initcall(favr32_init);
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