2f5997140f
Migrate the PIT timer to the physical CPU which vcpu0 is scheduled on, similarly to what is done for the LAPIC timers, otherwise PIT interrupts will be delayed until an unrelated event causes an exit. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/*
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* irq.h: in kernel interrupt controller related definitions
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* Copyright (c) 2007, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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* Authors:
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* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
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*
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*/
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#ifndef __IRQ_H
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#define __IRQ_H
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#include <linux/mm_types.h>
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#include <linux/hrtimer.h>
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#include <linux/kvm_host.h>
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#include "iodev.h"
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#include "ioapic.h"
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#include "lapic.h"
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struct kvm;
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struct kvm_vcpu;
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typedef void irq_request_func(void *opaque, int level);
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struct kvm_kpic_state {
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u8 last_irr; /* edge detection */
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u8 irr; /* interrupt request register */
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u8 imr; /* interrupt mask register */
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u8 isr; /* interrupt service register */
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u8 priority_add; /* highest irq priority */
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u8 irq_base;
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u8 read_reg_select;
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u8 poll;
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u8 special_mask;
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u8 init_state;
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u8 auto_eoi;
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u8 rotate_on_auto_eoi;
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u8 special_fully_nested_mode;
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u8 init4; /* true if 4 byte init */
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u8 elcr; /* PIIX edge/trigger selection */
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u8 elcr_mask;
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struct kvm_pic *pics_state;
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};
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struct kvm_pic {
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struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
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irq_request_func *irq_request;
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void *irq_request_opaque;
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int output; /* intr from master PIC */
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struct kvm_io_device dev;
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};
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struct kvm_pic *kvm_create_pic(struct kvm *kvm);
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void kvm_pic_set_irq(void *opaque, int irq, int level);
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int kvm_pic_read_irq(struct kvm_pic *s);
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void kvm_pic_update_irq(struct kvm_pic *s);
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static inline struct kvm_pic *pic_irqchip(struct kvm *kvm)
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{
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return kvm->arch.vpic;
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}
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static inline int irqchip_in_kernel(struct kvm *kvm)
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{
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return pic_irqchip(kvm) != NULL;
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}
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void kvm_pic_reset(struct kvm_kpic_state *s);
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void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
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void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
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void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
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void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu);
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void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu);
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void __kvm_migrate_timers(struct kvm_vcpu *vcpu);
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int pit_has_pending_timer(struct kvm_vcpu *vcpu);
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int apic_has_pending_timer(struct kvm_vcpu *vcpu);
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#endif
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