18aecc2b64
This support was partially present in the existing code (look for "__tilegx__" ifdefs) but with this change you can build a working kernel using the TILE-Gx toolchain and ARCH=tilegx. Most of these files are new, generally adding a foo_64.c file where previously there was just a foo_32.c file. The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx, using the existing SRCARCH mechanism in the top-level Makefile. Changes to existing files: - <asm/bitops.h> and <asm/bitops_32.h> changed to factor the include of <asm-generic/bitops/non-atomic.h> in the common header. - <asm/compat.h> and arch/tile/kernel/compat.c changed to remove the "const" markers I had put on compat_sys_execve() when trying to match some recent similar changes to the non-compat execve. It turns out the compat version wasn't "upgraded" to use const. - <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were previously included accidentally, with the 32-bit contents. Now they have the proper 64-bit contents. Finally, I had to hack the existing hacky drivers/input/input-compat.h to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64). Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_BITOPS_64_H
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#define _ASM_TILE_BITOPS_64_H
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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/* See <asm/bitops.h> for API comments. */
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static inline void set_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long mask = (1UL << (nr % BITS_PER_LONG));
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__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
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}
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static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long mask = (1UL << (nr % BITS_PER_LONG));
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__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
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}
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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static inline void change_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long old, mask = (1UL << (nr % BITS_PER_LONG));
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long guess, oldval;
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addr += nr / BITS_PER_LONG;
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old = *addr;
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do {
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guess = oldval;
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oldval = atomic64_cmpxchg((atomic64_t *)addr,
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guess, guess ^ mask);
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} while (guess != oldval);
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}
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/*
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* The test_and_xxx_bit() routines require a memory fence before we
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* start the operation, and after the operation completes. We use
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* smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
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* barrier(), to block until the atomic op is complete.
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*/
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static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
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{
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int val;
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unsigned long mask = (1UL << (nr % BITS_PER_LONG));
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smp_mb(); /* barrier for proper semantics */
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val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
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& mask) != 0;
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barrier();
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return val;
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}
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static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
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{
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int val;
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unsigned long mask = (1UL << (nr % BITS_PER_LONG));
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smp_mb(); /* barrier for proper semantics */
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val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
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& mask) != 0;
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barrier();
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return val;
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}
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static inline int test_and_change_bit(unsigned nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = (1UL << (nr % BITS_PER_LONG));
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long guess, oldval = *addr;
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addr += nr / BITS_PER_LONG;
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oldval = *addr;
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do {
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guess = oldval;
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oldval = atomic64_cmpxchg((atomic64_t *)addr,
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guess, guess ^ mask);
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} while (guess != oldval);
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return (oldval & mask) != 0;
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}
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#define ext2_set_bit_atomic(lock, nr, addr) \
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test_and_set_bit((nr), (unsigned long *)(addr))
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#define ext2_clear_bit_atomic(lock, nr, addr) \
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test_and_clear_bit((nr), (unsigned long *)(addr))
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#endif /* _ASM_TILE_BITOPS_64_H */
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