55aaf6ecf7
This patch sets the ibpre flag (Inbound Presence) for the 405EX in the 4xx PCIe driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
1529 lines
41 KiB
C
1529 lines
41 KiB
C
/*
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* PCI / PCI-X / PCI-Express support for 4xx parts
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*
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* Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*
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* Most PCI Express code is coming from Stefan Roese implementation for
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* arch/ppc in the Denx tree, slightly reworked by me.
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*
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* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* Some of that comes itself from a previous implementation for 440SPE only
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* by Roland Dreier:
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*
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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* Roland Dreier <rolandd@cisco.com>
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*
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/bootmem.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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#include "ppc4xx_pci.h"
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static int dma_offset_set;
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/* Move that to a useable header */
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extern unsigned long total_memory;
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#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
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#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
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#ifdef CONFIG_RESOURCES_64BIT
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#define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val)
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#define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val)
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#else
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#define RES_TO_U32_LOW(val) (val)
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#define RES_TO_U32_HIGH(val) (0)
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#endif
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static inline int ppc440spe_revA(void)
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{
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/* Catch both 440SPe variants, with and without RAID6 support */
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if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
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return 1;
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else
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return 0;
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}
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static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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int i;
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if (dev->devfn != 0 || dev->bus->self != NULL)
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return;
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hose = pci_bus_to_host(dev->bus);
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if (hose == NULL)
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return;
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if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
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!of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
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!of_device_is_compatible(hose->dn, "ibm,plb-pci"))
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return;
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/* Hide the PCI host BARs from the kernel as their content doesn't
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* fit well in the resource management
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*/
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
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pci_name(dev));
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
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static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
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void __iomem *reg,
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struct resource *res)
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{
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u64 size;
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const u32 *ranges;
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int rlen;
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int pna = of_n_addr_cells(hose->dn);
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int np = pna + 5;
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/* Default */
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res->start = 0;
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res->end = size = 0x80000000;
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res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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/* Get dma-ranges property */
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ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
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if (ranges == NULL)
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goto out;
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/* Walk it */
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while ((rlen -= np * 4) >= 0) {
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u32 pci_space = ranges[0];
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u64 pci_addr = of_read_number(ranges + 1, 2);
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u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
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size = of_read_number(ranges + pna + 3, 2);
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ranges += np;
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if (cpu_addr == OF_BAD_ADDR || size == 0)
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continue;
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/* We only care about memory */
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if ((pci_space & 0x03000000) != 0x02000000)
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continue;
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/* We currently only support memory at 0, and pci_addr
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* within 32 bits space
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*/
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if (cpu_addr != 0 || pci_addr > 0xffffffff) {
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printk(KERN_WARNING "%s: Ignored unsupported dma range"
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" 0x%016llx...0x%016llx -> 0x%016llx\n",
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hose->dn->full_name,
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pci_addr, pci_addr + size - 1, cpu_addr);
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continue;
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}
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/* Check if not prefetchable */
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if (!(pci_space & 0x40000000))
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res->flags &= ~IORESOURCE_PREFETCH;
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/* Use that */
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res->start = pci_addr;
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#ifndef CONFIG_RESOURCES_64BIT
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/* Beware of 32 bits resources */
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if ((pci_addr + size) > 0x100000000ull)
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res->end = 0xffffffff;
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else
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#endif
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res->end = res->start + size - 1;
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break;
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}
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/* We only support one global DMA offset */
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if (dma_offset_set && pci_dram_offset != res->start) {
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printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
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hose->dn->full_name);
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return -ENXIO;
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}
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/* Check that we can fit all of memory as we don't support
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* DMA bounce buffers
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*/
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if (size < total_memory) {
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printk(KERN_ERR "%s: dma-ranges too small "
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"(size=%llx total_memory=%lx)\n",
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hose->dn->full_name, size, total_memory);
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return -ENXIO;
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}
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/* Check we are a power of 2 size and that base is a multiple of size*/
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if (!is_power_of_2(size) ||
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(res->start & (size - 1)) != 0) {
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printk(KERN_ERR "%s: dma-ranges unaligned\n",
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hose->dn->full_name);
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return -ENXIO;
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}
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/* Check that we are fully contained within 32 bits space */
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if (res->end > 0xffffffff) {
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printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
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hose->dn->full_name);
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return -ENXIO;
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}
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out:
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dma_offset_set = 1;
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pci_dram_offset = res->start;
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printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
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pci_dram_offset);
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return 0;
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}
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/*
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* 4xx PCI 2.x part
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*/
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static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
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void __iomem *reg)
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{
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u32 la, ma, pcila, pciha;
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int i, j;
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/* Setup outbound memory windows */
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for (i = j = 0; i < 3; i++) {
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struct resource *res = &hose->mem_resources[i];
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/* we only care about memory windows */
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if (!(res->flags & IORESOURCE_MEM))
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continue;
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if (j > 2) {
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printk(KERN_WARNING "%s: Too many ranges\n",
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hose->dn->full_name);
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break;
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}
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/* Calculate register values */
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la = res->start;
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pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
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pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
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ma = res->end + 1 - res->start;
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if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
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printk(KERN_WARNING "%s: Resource out of range\n",
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hose->dn->full_name);
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continue;
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}
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ma = (0xffffffffu << ilog2(ma)) | 0x1;
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if (res->flags & IORESOURCE_PREFETCH)
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ma |= 0x2;
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/* Program register values */
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writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
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writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
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writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
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writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
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j++;
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}
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}
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static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
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void __iomem *reg,
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const struct resource *res)
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{
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resource_size_t size = res->end - res->start + 1;
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u32 sa;
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/* Calculate window size */
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sa = (0xffffffffu << ilog2(size)) | 1;
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sa |= 0x1;
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/* RAM is always at 0 local for now */
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writel(0, reg + PCIL0_PTM1LA);
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writel(sa, reg + PCIL0_PTM1MS);
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/* Map on PCI side */
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early_write_config_dword(hose, hose->first_busno, 0,
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PCI_BASE_ADDRESS_1, res->start);
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early_write_config_dword(hose, hose->first_busno, 0,
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PCI_BASE_ADDRESS_2, 0x00000000);
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early_write_config_word(hose, hose->first_busno, 0,
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PCI_COMMAND, 0x0006);
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}
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static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
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{
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/* NYI */
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struct resource rsrc_cfg;
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struct resource rsrc_reg;
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struct resource dma_window;
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struct pci_controller *hose = NULL;
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void __iomem *reg = NULL;
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const int *bus_range;
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int primary = 0;
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/* Fetch config space registers address */
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if (of_address_to_resource(np, 0, &rsrc_cfg)) {
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printk(KERN_ERR "%s:Can't get PCI config register base !",
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np->full_name);
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return;
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}
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/* Fetch host bridge internal registers address */
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if (of_address_to_resource(np, 3, &rsrc_reg)) {
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printk(KERN_ERR "%s: Can't get PCI internal register base !",
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np->full_name);
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return;
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}
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/* Check if primary bridge */
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if (of_get_property(np, "primary", NULL))
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primary = 1;
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/* Get bus range if any */
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bus_range = of_get_property(np, "bus-range", NULL);
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/* Map registers */
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reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
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if (reg == NULL) {
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printk(KERN_ERR "%s: Can't map registers !", np->full_name);
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goto fail;
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}
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/* Allocate the host controller data structure */
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hose = pcibios_alloc_controller(np);
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if (!hose)
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goto fail;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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/* Setup config space */
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setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
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/* Disable all windows */
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writel(0, reg + PCIL0_PMM0MA);
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writel(0, reg + PCIL0_PMM1MA);
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writel(0, reg + PCIL0_PMM2MA);
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writel(0, reg + PCIL0_PTM1MS);
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writel(0, reg + PCIL0_PTM2MS);
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/* Parse outbound mapping resources */
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pci_process_bridge_OF_ranges(hose, np, primary);
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/* Parse inbound mapping resources */
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if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
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goto fail;
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/* Configure outbound ranges POMs */
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ppc4xx_configure_pci_PMMs(hose, reg);
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/* Configure inbound ranges PIMs */
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ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
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/* We don't need the registers anymore */
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iounmap(reg);
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return;
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fail:
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if (hose)
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pcibios_free_controller(hose);
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if (reg)
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iounmap(reg);
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}
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/*
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* 4xx PCI-X part
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*/
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static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
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void __iomem *reg)
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{
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u32 lah, lal, pciah, pcial, sa;
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int i, j;
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/* Setup outbound memory windows */
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for (i = j = 0; i < 3; i++) {
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struct resource *res = &hose->mem_resources[i];
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/* we only care about memory windows */
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if (!(res->flags & IORESOURCE_MEM))
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continue;
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if (j > 1) {
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printk(KERN_WARNING "%s: Too many ranges\n",
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hose->dn->full_name);
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break;
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}
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/* Calculate register values */
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lah = RES_TO_U32_HIGH(res->start);
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lal = RES_TO_U32_LOW(res->start);
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pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
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pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
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sa = res->end + 1 - res->start;
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if (!is_power_of_2(sa) || sa < 0x100000 ||
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sa > 0xffffffffu) {
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printk(KERN_WARNING "%s: Resource out of range\n",
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hose->dn->full_name);
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continue;
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}
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sa = (0xffffffffu << ilog2(sa)) | 0x1;
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/* Program register values */
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if (j == 0) {
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writel(lah, reg + PCIX0_POM0LAH);
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writel(lal, reg + PCIX0_POM0LAL);
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writel(pciah, reg + PCIX0_POM0PCIAH);
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writel(pcial, reg + PCIX0_POM0PCIAL);
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writel(sa, reg + PCIX0_POM0SA);
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} else {
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writel(lah, reg + PCIX0_POM1LAH);
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writel(lal, reg + PCIX0_POM1LAL);
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writel(pciah, reg + PCIX0_POM1PCIAH);
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writel(pcial, reg + PCIX0_POM1PCIAL);
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writel(sa, reg + PCIX0_POM1SA);
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}
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j++;
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}
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}
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static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
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void __iomem *reg,
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const struct resource *res,
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int big_pim,
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int enable_msi_hole)
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{
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resource_size_t size = res->end - res->start + 1;
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u32 sa;
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/* RAM is always at 0 */
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writel(0x00000000, reg + PCIX0_PIM0LAH);
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writel(0x00000000, reg + PCIX0_PIM0LAL);
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/* Calculate window size */
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sa = (0xffffffffu << ilog2(size)) | 1;
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sa |= 0x1;
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if (res->flags & IORESOURCE_PREFETCH)
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sa |= 0x2;
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if (enable_msi_hole)
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sa |= 0x4;
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writel(sa, reg + PCIX0_PIM0SA);
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if (big_pim)
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writel(0xffffffff, reg + PCIX0_PIM0SAH);
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/* Map on PCI side */
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writel(0x00000000, reg + PCIX0_BAR0H);
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writel(res->start, reg + PCIX0_BAR0L);
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writew(0x0006, reg + PCIX0_COMMAND);
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}
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|
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static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
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{
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struct resource rsrc_cfg;
|
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struct resource rsrc_reg;
|
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struct resource dma_window;
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struct pci_controller *hose = NULL;
|
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void __iomem *reg = NULL;
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const int *bus_range;
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int big_pim = 0, msi = 0, primary = 0;
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|
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/* Fetch config space registers address */
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if (of_address_to_resource(np, 0, &rsrc_cfg)) {
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printk(KERN_ERR "%s:Can't get PCI-X config register base !",
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np->full_name);
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return;
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}
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/* Fetch host bridge internal registers address */
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if (of_address_to_resource(np, 3, &rsrc_reg)) {
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printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
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np->full_name);
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return;
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}
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|
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/* Check if it supports large PIMs (440GX) */
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if (of_get_property(np, "large-inbound-windows", NULL))
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big_pim = 1;
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|
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/* Check if we should enable MSIs inbound hole */
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if (of_get_property(np, "enable-msi-hole", NULL))
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msi = 1;
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|
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/* Check if primary bridge */
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if (of_get_property(np, "primary", NULL))
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primary = 1;
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|
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/* Get bus range if any */
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bus_range = of_get_property(np, "bus-range", NULL);
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|
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/* Map registers */
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reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
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if (reg == NULL) {
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printk(KERN_ERR "%s: Can't map registers !", np->full_name);
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goto fail;
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}
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|
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/* Allocate the host controller data structure */
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hose = pcibios_alloc_controller(np);
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if (!hose)
|
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goto fail;
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|
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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|
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/* Setup config space */
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setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
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|
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/* Disable all windows */
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writel(0, reg + PCIX0_POM0SA);
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writel(0, reg + PCIX0_POM1SA);
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writel(0, reg + PCIX0_POM2SA);
|
|
writel(0, reg + PCIX0_PIM0SA);
|
|
writel(0, reg + PCIX0_PIM1SA);
|
|
writel(0, reg + PCIX0_PIM2SA);
|
|
if (big_pim) {
|
|
writel(0, reg + PCIX0_PIM0SAH);
|
|
writel(0, reg + PCIX0_PIM2SAH);
|
|
}
|
|
|
|
/* Parse outbound mapping resources */
|
|
pci_process_bridge_OF_ranges(hose, np, primary);
|
|
|
|
/* Parse inbound mapping resources */
|
|
if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
|
|
goto fail;
|
|
|
|
/* Configure outbound ranges POMs */
|
|
ppc4xx_configure_pcix_POMs(hose, reg);
|
|
|
|
/* Configure inbound ranges PIMs */
|
|
ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
|
|
|
|
/* We don't need the registers anymore */
|
|
iounmap(reg);
|
|
return;
|
|
|
|
fail:
|
|
if (hose)
|
|
pcibios_free_controller(hose);
|
|
if (reg)
|
|
iounmap(reg);
|
|
}
|
|
|
|
#ifdef CONFIG_PPC4xx_PCI_EXPRESS
|
|
|
|
/*
|
|
* 4xx PCI-Express part
|
|
*
|
|
* We support 3 parts currently based on the compatible property:
|
|
*
|
|
* ibm,plb-pciex-440spe
|
|
* ibm,plb-pciex-405ex
|
|
*
|
|
* Anything else will be rejected for now as they are all subtly
|
|
* different unfortunately.
|
|
*
|
|
*/
|
|
|
|
#define MAX_PCIE_BUS_MAPPED 0x10
|
|
|
|
struct ppc4xx_pciex_port
|
|
{
|
|
struct pci_controller *hose;
|
|
struct device_node *node;
|
|
unsigned int index;
|
|
int endpoint;
|
|
int link;
|
|
int has_ibpre;
|
|
unsigned int sdr_base;
|
|
dcr_host_t dcrs;
|
|
struct resource cfg_space;
|
|
struct resource utl_regs;
|
|
void __iomem *utl_base;
|
|
};
|
|
|
|
static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
|
|
static unsigned int ppc4xx_pciex_port_count;
|
|
|
|
struct ppc4xx_pciex_hwops
|
|
{
|
|
int (*core_init)(struct device_node *np);
|
|
int (*port_init_hw)(struct ppc4xx_pciex_port *port);
|
|
int (*setup_utl)(struct ppc4xx_pciex_port *port);
|
|
};
|
|
|
|
static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
|
|
|
|
#ifdef CONFIG_44x
|
|
|
|
/* Check various reset bits of the 440SPe PCIe core */
|
|
static int __init ppc440spe_pciex_check_reset(struct device_node *np)
|
|
{
|
|
u32 valPE0, valPE1, valPE2;
|
|
int err = 0;
|
|
|
|
/* SDR0_PEGPLLLCT1 reset */
|
|
if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
|
|
/*
|
|
* the PCIe core was probably already initialised
|
|
* by firmware - let's re-reset RCSSET regs
|
|
*
|
|
* -- Shouldn't we also re-reset the whole thing ? -- BenH
|
|
*/
|
|
pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
|
|
mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
|
|
mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
|
|
mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
|
|
}
|
|
|
|
valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
|
|
valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
|
|
valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
|
|
|
|
/* SDR0_PExRCSSET rstgu */
|
|
if (!(valPE0 & 0x01000000) ||
|
|
!(valPE1 & 0x01000000) ||
|
|
!(valPE2 & 0x01000000)) {
|
|
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
|
|
err = -1;
|
|
}
|
|
|
|
/* SDR0_PExRCSSET rstdl */
|
|
if (!(valPE0 & 0x00010000) ||
|
|
!(valPE1 & 0x00010000) ||
|
|
!(valPE2 & 0x00010000)) {
|
|
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
|
|
err = -1;
|
|
}
|
|
|
|
/* SDR0_PExRCSSET rstpyn */
|
|
if ((valPE0 & 0x00001000) ||
|
|
(valPE1 & 0x00001000) ||
|
|
(valPE2 & 0x00001000)) {
|
|
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
|
|
err = -1;
|
|
}
|
|
|
|
/* SDR0_PExRCSSET hldplb */
|
|
if ((valPE0 & 0x10000000) ||
|
|
(valPE1 & 0x10000000) ||
|
|
(valPE2 & 0x10000000)) {
|
|
printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
|
|
err = -1;
|
|
}
|
|
|
|
/* SDR0_PExRCSSET rdy */
|
|
if ((valPE0 & 0x00100000) ||
|
|
(valPE1 & 0x00100000) ||
|
|
(valPE2 & 0x00100000)) {
|
|
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
|
|
err = -1;
|
|
}
|
|
|
|
/* SDR0_PExRCSSET shutdown */
|
|
if ((valPE0 & 0x00000100) ||
|
|
(valPE1 & 0x00000100) ||
|
|
(valPE2 & 0x00000100)) {
|
|
printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
|
|
err = -1;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/* Global PCIe core initializations for 440SPe core */
|
|
static int __init ppc440spe_pciex_core_init(struct device_node *np)
|
|
{
|
|
int time_out = 20;
|
|
|
|
/* Set PLL clock receiver to LVPECL */
|
|
mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
|
|
|
|
/* Shouldn't we do all the calibration stuff etc... here ? */
|
|
if (ppc440spe_pciex_check_reset(np))
|
|
return -ENXIO;
|
|
|
|
if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
|
|
printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
|
|
"failed (0x%08x)\n",
|
|
mfdcri(SDR0, PESDR0_PLLLCT2));
|
|
return -1;
|
|
}
|
|
|
|
/* De-assert reset of PCIe PLL, wait for lock */
|
|
mtdcri(SDR0, PESDR0_PLLLCT1,
|
|
mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
|
|
udelay(3);
|
|
|
|
while (time_out) {
|
|
if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
|
|
time_out--;
|
|
udelay(1);
|
|
} else
|
|
break;
|
|
}
|
|
if (!time_out) {
|
|
printk(KERN_INFO "PCIE: VCO output not locked\n");
|
|
return -1;
|
|
}
|
|
|
|
pr_debug("PCIE initialization OK\n");
|
|
|
|
return 3;
|
|
}
|
|
|
|
static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
|
{
|
|
u32 val = 1 << 24;
|
|
|
|
if (port->endpoint)
|
|
val = PTYPE_LEGACY_ENDPOINT << 20;
|
|
else
|
|
val = PTYPE_ROOT_PORT << 20;
|
|
|
|
if (port->index == 0)
|
|
val |= LNKW_X8 << 12;
|
|
else
|
|
val |= LNKW_X4 << 12;
|
|
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
|
|
if (ppc440spe_revA())
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
|
|
if (port->index == 0) {
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
|
|
0x35000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
|
|
0x35000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
|
|
0x35000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
|
|
0x35000000);
|
|
}
|
|
val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
|
|
(val & ~(1 << 24 | 1 << 16)) | 1 << 12);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
|
{
|
|
return ppc440spe_pciex_init_port_hw(port);
|
|
}
|
|
|
|
static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
|
{
|
|
int rc = ppc440spe_pciex_init_port_hw(port);
|
|
|
|
port->has_ibpre = 1;
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
|
{
|
|
/* XXX Check what that value means... I hate magic */
|
|
dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
|
|
|
|
/*
|
|
* Set buffer allocations and then assert VRB and TXE.
|
|
*/
|
|
out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
|
|
out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
|
|
out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
|
|
out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
|
|
out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
|
|
out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
|
|
out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
|
|
out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
|
{
|
|
/* Report CRS to the operating system */
|
|
out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
|
|
{
|
|
.core_init = ppc440spe_pciex_core_init,
|
|
.port_init_hw = ppc440speA_pciex_init_port_hw,
|
|
.setup_utl = ppc440speA_pciex_init_utl,
|
|
};
|
|
|
|
static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
|
|
{
|
|
.core_init = ppc440spe_pciex_core_init,
|
|
.port_init_hw = ppc440speB_pciex_init_port_hw,
|
|
.setup_utl = ppc440speB_pciex_init_utl,
|
|
};
|
|
|
|
#endif /* CONFIG_44x */
|
|
|
|
#ifdef CONFIG_40x
|
|
|
|
static int __init ppc405ex_pciex_core_init(struct device_node *np)
|
|
{
|
|
/* Nothing to do, return 2 ports */
|
|
return 2;
|
|
}
|
|
|
|
static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
|
|
{
|
|
/* Assert the PE0_PHY reset */
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
|
|
msleep(1);
|
|
|
|
/* deassert the PE0_hotreset */
|
|
if (port->endpoint)
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
|
|
else
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
|
|
|
|
/* poll for phy !reset */
|
|
/* XXX FIXME add timeout */
|
|
while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
|
|
;
|
|
|
|
/* deassert the PE0_gpl_utl_reset */
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
|
|
}
|
|
|
|
static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
|
{
|
|
u32 val;
|
|
|
|
if (port->endpoint)
|
|
val = PTYPE_LEGACY_ENDPOINT;
|
|
else
|
|
val = PTYPE_ROOT_PORT;
|
|
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
|
|
1 << 24 | val << 20 | LNKW_X1 << 12);
|
|
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
|
|
|
|
/*
|
|
* Only reset the PHY when no link is currently established.
|
|
* This is for the Atheros PCIe board which has problems to establish
|
|
* the link (again) after this PHY reset. All other currently tested
|
|
* PCIe boards don't show this problem.
|
|
* This has to be re-tested and fixed in a later release!
|
|
*/
|
|
#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
|
|
* configured as done previously by U-Boot. Then Linux will currently
|
|
* not reassign them. So the PHY reset is now done always. This will
|
|
* lead to problems with the Atheros PCIe board again.
|
|
*/
|
|
val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
|
|
if (!(val & 0x00001000))
|
|
ppc405ex_pcie_phy_reset(port);
|
|
#else
|
|
ppc405ex_pcie_phy_reset(port);
|
|
#endif
|
|
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
|
|
|
|
port->has_ibpre = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
|
{
|
|
dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
|
|
|
|
/*
|
|
* Set buffer allocations and then assert VRB and TXE.
|
|
*/
|
|
out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
|
|
out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
|
|
out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
|
|
out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
|
|
out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
|
|
out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
|
|
out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
|
|
out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
|
|
|
|
out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
|
|
{
|
|
.core_init = ppc405ex_pciex_core_init,
|
|
.port_init_hw = ppc405ex_pciex_init_port_hw,
|
|
.setup_utl = ppc405ex_pciex_init_utl,
|
|
};
|
|
|
|
#endif /* CONFIG_40x */
|
|
|
|
|
|
/* Check that the core has been initied and if not, do it */
|
|
static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
|
|
{
|
|
static int core_init;
|
|
int count = -ENODEV;
|
|
|
|
if (core_init++)
|
|
return 0;
|
|
|
|
#ifdef CONFIG_44x
|
|
if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
|
|
if (ppc440spe_revA())
|
|
ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
|
|
else
|
|
ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
|
|
}
|
|
#endif /* CONFIG_44x */
|
|
#ifdef CONFIG_40x
|
|
if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
|
|
ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
|
|
#endif
|
|
if (ppc4xx_pciex_hwops == NULL) {
|
|
printk(KERN_WARNING "PCIE: unknown host type %s\n",
|
|
np->full_name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
count = ppc4xx_pciex_hwops->core_init(np);
|
|
if (count > 0) {
|
|
ppc4xx_pciex_ports =
|
|
kzalloc(count * sizeof(struct ppc4xx_pciex_port),
|
|
GFP_KERNEL);
|
|
if (ppc4xx_pciex_ports) {
|
|
ppc4xx_pciex_port_count = count;
|
|
return 0;
|
|
}
|
|
printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
|
|
return -ENOMEM;
|
|
}
|
|
return -ENODEV;
|
|
}
|
|
|
|
static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
|
|
{
|
|
/* We map PCI Express configuration based on the reg property */
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
|
|
RES_TO_U32_HIGH(port->cfg_space.start));
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
|
|
RES_TO_U32_LOW(port->cfg_space.start));
|
|
|
|
/* XXX FIXME: Use size from reg property. For now, map 512M */
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
|
|
|
|
/* We map UTL registers based on the reg property */
|
|
dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
|
|
RES_TO_U32_HIGH(port->utl_regs.start));
|
|
dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
|
|
RES_TO_U32_LOW(port->utl_regs.start));
|
|
|
|
/* XXX FIXME: Use size from reg property */
|
|
dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
|
|
|
|
/* Disable all other outbound windows */
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
|
|
}
|
|
|
|
static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
|
|
unsigned int sdr_offset,
|
|
unsigned int mask,
|
|
unsigned int value,
|
|
int timeout_ms)
|
|
{
|
|
u32 val;
|
|
|
|
while(timeout_ms--) {
|
|
val = mfdcri(SDR0, port->sdr_base + sdr_offset);
|
|
if ((val & mask) == value) {
|
|
pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
|
|
port->index, sdr_offset, timeout_ms, val);
|
|
return 0;
|
|
}
|
|
msleep(1);
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
|
|
{
|
|
int rc = 0;
|
|
|
|
/* Init HW */
|
|
if (ppc4xx_pciex_hwops->port_init_hw)
|
|
rc = ppc4xx_pciex_hwops->port_init_hw(port);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
printk(KERN_INFO "PCIE%d: Checking link...\n",
|
|
port->index);
|
|
|
|
/* Wait for reset to complete */
|
|
if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
|
|
printk(KERN_WARNING "PCIE%d: PGRST failed\n",
|
|
port->index);
|
|
return -1;
|
|
}
|
|
|
|
/* Check for card presence detect if supported, if not, just wait for
|
|
* link unconditionally.
|
|
*
|
|
* note that we don't fail if there is no link, we just filter out
|
|
* config space accesses. That way, it will be easier to implement
|
|
* hotplug later on.
|
|
*/
|
|
if (!port->has_ibpre ||
|
|
!ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
|
|
1 << 28, 1 << 28, 100)) {
|
|
printk(KERN_INFO
|
|
"PCIE%d: Device detected, waiting for link...\n",
|
|
port->index);
|
|
if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
|
|
0x1000, 0x1000, 2000))
|
|
printk(KERN_WARNING
|
|
"PCIE%d: Link up failed\n", port->index);
|
|
else {
|
|
printk(KERN_INFO
|
|
"PCIE%d: link is up !\n", port->index);
|
|
port->link = 1;
|
|
}
|
|
} else
|
|
printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
|
|
|
|
/*
|
|
* Initialize mapping: disable all regions and configure
|
|
* CFG and REG regions based on resources in the device tree
|
|
*/
|
|
ppc4xx_pciex_port_init_mapping(port);
|
|
|
|
/*
|
|
* Map UTL
|
|
*/
|
|
port->utl_base = ioremap(port->utl_regs.start, 0x100);
|
|
BUG_ON(port->utl_base == NULL);
|
|
|
|
/*
|
|
* Setup UTL registers --BenH.
|
|
*/
|
|
if (ppc4xx_pciex_hwops->setup_utl)
|
|
ppc4xx_pciex_hwops->setup_utl(port);
|
|
|
|
/*
|
|
* Check for VC0 active and assert RDY.
|
|
*/
|
|
if (port->link &&
|
|
ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
|
|
1 << 16, 1 << 16, 5000)) {
|
|
printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
|
|
port->link = 0;
|
|
}
|
|
|
|
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
|
|
mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
|
|
msleep(100);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
|
|
struct pci_bus *bus,
|
|
unsigned int devfn)
|
|
{
|
|
static int message;
|
|
|
|
/* Endpoint can not generate upstream(remote) config cycles */
|
|
if (port->endpoint && bus->number != port->hose->first_busno)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/* Check we are within the mapped range */
|
|
if (bus->number > port->hose->last_busno) {
|
|
if (!message) {
|
|
printk(KERN_WARNING "Warning! Probing bus %u"
|
|
" out of range !\n", bus->number);
|
|
message++;
|
|
}
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
/* The root complex has only one device / function */
|
|
if (bus->number == port->hose->first_busno && devfn != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/* The other side of the RC has only one device as well */
|
|
if (bus->number == (port->hose->first_busno + 1) &&
|
|
PCI_SLOT(devfn) != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/* Check if we have a link */
|
|
if ((bus->number != port->hose->first_busno) && !port->link)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
|
|
struct pci_bus *bus,
|
|
unsigned int devfn)
|
|
{
|
|
int relbus;
|
|
|
|
/* Remove the casts when we finally remove the stupid volatile
|
|
* in struct pci_controller
|
|
*/
|
|
if (bus->number == port->hose->first_busno)
|
|
return (void __iomem *)port->hose->cfg_addr;
|
|
|
|
relbus = bus->number - (port->hose->first_busno + 1);
|
|
return (void __iomem *)port->hose->cfg_data +
|
|
((relbus << 20) | (devfn << 12));
|
|
}
|
|
|
|
static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int len, u32 *val)
|
|
{
|
|
struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
|
|
struct ppc4xx_pciex_port *port =
|
|
&ppc4xx_pciex_ports[hose->indirect_type];
|
|
void __iomem *addr;
|
|
u32 gpl_cfg;
|
|
|
|
BUG_ON(hose != port->hose);
|
|
|
|
if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
|
|
|
|
/*
|
|
* Reading from configuration space of non-existing device can
|
|
* generate transaction errors. For the read duration we suppress
|
|
* assertion of machine check exceptions to avoid those.
|
|
*/
|
|
gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
|
|
|
|
/* Make sure no CRS is recorded */
|
|
out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
|
|
|
|
switch (len) {
|
|
case 1:
|
|
*val = in_8((u8 *)(addr + offset));
|
|
break;
|
|
case 2:
|
|
*val = in_le16((u16 *)(addr + offset));
|
|
break;
|
|
default:
|
|
*val = in_le32((u32 *)(addr + offset));
|
|
break;
|
|
}
|
|
|
|
pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
|
|
" offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
|
|
bus->number, hose->first_busno, hose->last_busno,
|
|
devfn, offset, len, addr + offset, *val);
|
|
|
|
/* Check for CRS (440SPe rev B does that for us but heh ..) */
|
|
if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
|
|
pr_debug("Got CRS !\n");
|
|
if (len != 4 || offset != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
*val = 0xffff0001;
|
|
}
|
|
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int len, u32 val)
|
|
{
|
|
struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
|
|
struct ppc4xx_pciex_port *port =
|
|
&ppc4xx_pciex_ports[hose->indirect_type];
|
|
void __iomem *addr;
|
|
u32 gpl_cfg;
|
|
|
|
if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
|
|
|
|
/*
|
|
* Reading from configuration space of non-existing device can
|
|
* generate transaction errors. For the read duration we suppress
|
|
* assertion of machine check exceptions to avoid those.
|
|
*/
|
|
gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
|
|
|
|
pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
|
|
" offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
|
|
bus->number, hose->first_busno, hose->last_busno,
|
|
devfn, offset, len, addr + offset, val);
|
|
|
|
switch (len) {
|
|
case 1:
|
|
out_8((u8 *)(addr + offset), val);
|
|
break;
|
|
case 2:
|
|
out_le16((u16 *)(addr + offset), val);
|
|
break;
|
|
default:
|
|
out_le32((u32 *)(addr + offset), val);
|
|
break;
|
|
}
|
|
|
|
dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static struct pci_ops ppc4xx_pciex_pci_ops =
|
|
{
|
|
.read = ppc4xx_pciex_read_config,
|
|
.write = ppc4xx_pciex_write_config,
|
|
};
|
|
|
|
static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
|
|
struct pci_controller *hose,
|
|
void __iomem *mbase)
|
|
{
|
|
u32 lah, lal, pciah, pcial, sa;
|
|
int i, j;
|
|
|
|
/* Setup outbound memory windows */
|
|
for (i = j = 0; i < 3; i++) {
|
|
struct resource *res = &hose->mem_resources[i];
|
|
|
|
/* we only care about memory windows */
|
|
if (!(res->flags & IORESOURCE_MEM))
|
|
continue;
|
|
if (j > 1) {
|
|
printk(KERN_WARNING "%s: Too many ranges\n",
|
|
port->node->full_name);
|
|
break;
|
|
}
|
|
|
|
/* Calculate register values */
|
|
lah = RES_TO_U32_HIGH(res->start);
|
|
lal = RES_TO_U32_LOW(res->start);
|
|
pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
|
|
pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
|
|
sa = res->end + 1 - res->start;
|
|
if (!is_power_of_2(sa) || sa < 0x100000 ||
|
|
sa > 0xffffffffu) {
|
|
printk(KERN_WARNING "%s: Resource out of range\n",
|
|
port->node->full_name);
|
|
continue;
|
|
}
|
|
sa = (0xffffffffu << ilog2(sa)) | 0x1;
|
|
|
|
/* Program register values */
|
|
switch (j) {
|
|
case 0:
|
|
out_le32(mbase + PECFG_POM0LAH, pciah);
|
|
out_le32(mbase + PECFG_POM0LAL, pcial);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
|
|
break;
|
|
case 1:
|
|
out_le32(mbase + PECFG_POM1LAH, pciah);
|
|
out_le32(mbase + PECFG_POM1LAL, pcial);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
|
|
break;
|
|
}
|
|
j++;
|
|
}
|
|
|
|
/* Configure IO, always 64K starting at 0 */
|
|
if (hose->io_resource.flags & IORESOURCE_IO) {
|
|
lah = RES_TO_U32_HIGH(hose->io_base_phys);
|
|
lal = RES_TO_U32_LOW(hose->io_base_phys);
|
|
out_le32(mbase + PECFG_POM2LAH, 0);
|
|
out_le32(mbase + PECFG_POM2LAL, 0);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
|
|
dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
|
|
}
|
|
}
|
|
|
|
static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
|
|
struct pci_controller *hose,
|
|
void __iomem *mbase,
|
|
struct resource *res)
|
|
{
|
|
resource_size_t size = res->end - res->start + 1;
|
|
u64 sa;
|
|
|
|
/* Calculate window size */
|
|
sa = (0xffffffffffffffffull << ilog2(size));;
|
|
if (res->flags & IORESOURCE_PREFETCH)
|
|
sa |= 0x8;
|
|
|
|
out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
|
|
out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
|
|
|
|
/* The setup of the split looks weird to me ... let's see if it works */
|
|
out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
|
|
out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
|
|
out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
|
|
out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
|
|
out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
|
|
out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
|
|
|
|
/* Enable inbound mapping */
|
|
out_le32(mbase + PECFG_PIMEN, 0x1);
|
|
|
|
out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
|
|
out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
|
|
|
|
/* Enable I/O, Mem, and Busmaster cycles */
|
|
out_le16(mbase + PCI_COMMAND,
|
|
in_le16(mbase + PCI_COMMAND) |
|
|
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
}
|
|
|
|
static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
|
|
{
|
|
struct resource dma_window;
|
|
struct pci_controller *hose = NULL;
|
|
const int *bus_range;
|
|
int primary = 0, busses;
|
|
void __iomem *mbase = NULL, *cfg_data = NULL;
|
|
|
|
/* XXX FIXME: Handle endpoint mode properly */
|
|
if (port->endpoint) {
|
|
printk(KERN_WARNING "PCIE%d: Port in endpoint mode !\n",
|
|
port->index);
|
|
return;
|
|
}
|
|
|
|
/* Check if primary bridge */
|
|
if (of_get_property(port->node, "primary", NULL))
|
|
primary = 1;
|
|
|
|
/* Get bus range if any */
|
|
bus_range = of_get_property(port->node, "bus-range", NULL);
|
|
|
|
/* Allocate the host controller data structure */
|
|
hose = pcibios_alloc_controller(port->node);
|
|
if (!hose)
|
|
goto fail;
|
|
|
|
/* We stick the port number in "indirect_type" so the config space
|
|
* ops can retrieve the port data structure easily
|
|
*/
|
|
hose->indirect_type = port->index;
|
|
|
|
/* Get bus range */
|
|
hose->first_busno = bus_range ? bus_range[0] : 0x0;
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
|
|
/* Because of how big mapping the config space is (1M per bus), we
|
|
* limit how many busses we support. In the long run, we could replace
|
|
* that with something akin to kmap_atomic instead. We set aside 1 bus
|
|
* for the host itself too.
|
|
*/
|
|
busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
|
|
if (busses > MAX_PCIE_BUS_MAPPED) {
|
|
busses = MAX_PCIE_BUS_MAPPED;
|
|
hose->last_busno = hose->first_busno + busses;
|
|
}
|
|
|
|
/* We map the external config space in cfg_data and the host config
|
|
* space in cfg_addr. External space is 1M per bus, internal space
|
|
* is 4K
|
|
*/
|
|
cfg_data = ioremap(port->cfg_space.start +
|
|
(hose->first_busno + 1) * 0x100000,
|
|
busses * 0x100000);
|
|
mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
|
|
if (cfg_data == NULL || mbase == NULL) {
|
|
printk(KERN_ERR "%s: Can't map config space !",
|
|
port->node->full_name);
|
|
goto fail;
|
|
}
|
|
|
|
hose->cfg_data = cfg_data;
|
|
hose->cfg_addr = mbase;
|
|
|
|
pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
|
|
hose->first_busno, hose->last_busno);
|
|
pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
|
|
hose->cfg_addr, hose->cfg_data);
|
|
|
|
/* Setup config space */
|
|
hose->ops = &ppc4xx_pciex_pci_ops;
|
|
port->hose = hose;
|
|
mbase = (void __iomem *)hose->cfg_addr;
|
|
|
|
/*
|
|
* Set bus numbers on our root port
|
|
*/
|
|
out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
|
|
out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
|
|
out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
|
|
|
|
/*
|
|
* OMRs are already reset, also disable PIMs
|
|
*/
|
|
out_le32(mbase + PECFG_PIMEN, 0);
|
|
|
|
/* Parse outbound mapping resources */
|
|
pci_process_bridge_OF_ranges(hose, port->node, primary);
|
|
|
|
/* Parse inbound mapping resources */
|
|
if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
|
|
goto fail;
|
|
|
|
/* Configure outbound ranges POMs */
|
|
ppc4xx_configure_pciex_POMs(port, hose, mbase);
|
|
|
|
/* Configure inbound ranges PIMs */
|
|
ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
|
|
|
|
/* The root complex doesn't show up if we don't set some vendor
|
|
* and device IDs into it. Those are the same bogus one that the
|
|
* initial code in arch/ppc add. We might want to change that.
|
|
*/
|
|
out_le16(mbase + 0x200, 0xaaa0 + port->index);
|
|
out_le16(mbase + 0x202, 0xbed0 + port->index);
|
|
|
|
/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
|
|
out_le32(mbase + 0x208, 0x06040001);
|
|
|
|
printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
|
|
port->index);
|
|
return;
|
|
fail:
|
|
if (hose)
|
|
pcibios_free_controller(hose);
|
|
if (cfg_data)
|
|
iounmap(cfg_data);
|
|
if (mbase)
|
|
iounmap(mbase);
|
|
}
|
|
|
|
static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
|
|
{
|
|
struct ppc4xx_pciex_port *port;
|
|
const u32 *pval;
|
|
int portno;
|
|
unsigned int dcrs;
|
|
|
|
/* First, proceed to core initialization as we assume there's
|
|
* only one PCIe core in the system
|
|
*/
|
|
if (ppc4xx_pciex_check_core_init(np))
|
|
return;
|
|
|
|
/* Get the port number from the device-tree */
|
|
pval = of_get_property(np, "port", NULL);
|
|
if (pval == NULL) {
|
|
printk(KERN_ERR "PCIE: Can't find port number for %s\n",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
portno = *pval;
|
|
if (portno >= ppc4xx_pciex_port_count) {
|
|
printk(KERN_ERR "PCIE: port number out of range for %s\n",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
port = &ppc4xx_pciex_ports[portno];
|
|
port->index = portno;
|
|
port->node = of_node_get(np);
|
|
pval = of_get_property(np, "sdr-base", NULL);
|
|
if (pval == NULL) {
|
|
printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
port->sdr_base = *pval;
|
|
|
|
/* XXX Currently, we only support root complex mode */
|
|
port->endpoint = 0;
|
|
|
|
/* Fetch config space registers address */
|
|
if (of_address_to_resource(np, 0, &port->cfg_space)) {
|
|
printk(KERN_ERR "%s: Can't get PCI-E config space !",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
/* Fetch host bridge internal registers address */
|
|
if (of_address_to_resource(np, 1, &port->utl_regs)) {
|
|
printk(KERN_ERR "%s: Can't get UTL register base !",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
|
|
/* Map DCRs */
|
|
dcrs = dcr_resource_start(np, 0);
|
|
if (dcrs == 0) {
|
|
printk(KERN_ERR "%s: Can't get DCR register base !",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
|
|
|
|
/* Initialize the port specific registers */
|
|
if (ppc4xx_pciex_port_init(port)) {
|
|
printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
|
|
return;
|
|
}
|
|
|
|
/* Setup the linux hose data structure */
|
|
ppc4xx_pciex_port_setup_hose(port);
|
|
}
|
|
|
|
#endif /* CONFIG_PPC4xx_PCI_EXPRESS */
|
|
|
|
static int __init ppc4xx_pci_find_bridges(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
#ifdef CONFIG_PPC4xx_PCI_EXPRESS
|
|
for_each_compatible_node(np, NULL, "ibm,plb-pciex")
|
|
ppc4xx_probe_pciex_bridge(np);
|
|
#endif
|
|
for_each_compatible_node(np, NULL, "ibm,plb-pcix")
|
|
ppc4xx_probe_pcix_bridge(np);
|
|
for_each_compatible_node(np, NULL, "ibm,plb-pci")
|
|
ppc4xx_probe_pci_bridge(np);
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(ppc4xx_pci_find_bridges);
|
|
|