0324f59fc9
The CHIRONSS has its own local PRCM module and the register defines need to use the CHIRONSS base and not the PRM base. The changes are generated by updating the script which autogenerates the file modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
395 lines
14 KiB
C
395 lines
14 KiB
C
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
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#define __ARCH_ARM_MACH_OMAP2_PRM_H
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/*
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* OMAP2/3 Power/Reset Management (PRM) register definitions
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*
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2009 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "prcm-common.h"
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#define OMAP2420_PRM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
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#define OMAP2430_PRM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
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#define OMAP34XX_PRM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
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#define OMAP44XX_PRM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
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#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
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#include "prm44xx.h"
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/*
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* Architecture-specific global PRM registers
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* Use __raw_{read,write}l() with these registers.
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*
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* With a few exceptions, these are the register names beginning with
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* PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
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* IRQSTATUS and IRQENABLE bits.)
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*
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*/
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#define OMAP2_PRCM_REVISION_OFFSET 0x0000
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#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
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#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
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#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
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#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
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#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
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#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
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#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
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#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
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#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
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#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
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#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
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#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
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#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
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#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
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#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
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#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
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#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
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#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
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#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
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#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
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#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
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#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
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#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
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#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
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#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
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#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
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#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
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#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
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#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
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#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
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#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
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#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
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#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
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#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
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#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
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#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
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#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
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#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
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#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
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#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
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#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
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#define OMAP3_PRM_REVISION_OFFSET 0x0004
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#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
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#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
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#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
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#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
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#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
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#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
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#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
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#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
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#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
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#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
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#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
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#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
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#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
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#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
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#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
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#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
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#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
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#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
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#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
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#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
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#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
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#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
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#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
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#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
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#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
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#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
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#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
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#define OMAP3_PRM_RSTST_OFFSET 0x0058
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#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
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#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
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#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
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#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
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#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
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#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
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#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
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#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
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#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
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#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
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#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
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#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
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#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
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#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
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#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
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#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
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#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
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#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
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#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
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#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
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#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
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#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
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#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
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#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
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#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
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#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
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#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
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#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
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#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
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#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
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#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
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#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
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#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
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#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
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#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
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#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
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#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
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#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
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#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
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#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
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#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
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#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
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#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
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#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
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#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
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/*
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* Module specific PRM registers from PRM_BASE + domain offset
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*
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* Use prm_{read,write}_mod_reg() with these registers.
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*
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* With a few exceptions, these are the register names beginning with
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* {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
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* and IRQENABLE bits.)
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*
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*/
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/* Registers appearing on both 24xx and 34xx */
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#define RM_RSTCTRL 0x0050
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#define RM_RSTTIME 0x0054
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#define RM_RSTST 0x0058
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#define PM_WKEN 0x00a0
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#define PM_WKEN1 PM_WKEN
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#define PM_WKST 0x00b0
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#define PM_WKST1 PM_WKST
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#define PM_WKDEP 0x00c8
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#define PM_EVGENCTRL 0x00d4
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#define PM_EVGENONTIM 0x00d8
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#define PM_EVGENOFFTIM 0x00dc
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#define PM_PWSTCTRL 0x00e0
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#define PM_PWSTST 0x00e4
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/* Omap2 specific registers */
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#define OMAP24XX_PM_WKEN2 0x00a4
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#define OMAP24XX_PM_WKST2 0x00b4
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#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
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#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
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#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
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#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
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/* Omap3 specific registers */
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#define OMAP3430ES2_PM_WKEN3 0x00f0
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#define OMAP3430ES2_PM_WKST3 0x00b8
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#define OMAP3430_PM_MPUGRPSEL 0x00a4
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#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
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#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
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#define OMAP3430_PM_IVAGRPSEL 0x00a8
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#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
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#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
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#define OMAP3430_PM_PREPWSTST 0x00e8
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#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
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#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
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#ifndef __ASSEMBLER__
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/* Power/reset management domain register get/set */
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extern u32 prm_read_mod_reg(s16 module, u16 idx);
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extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
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extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
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/* Read-modify-write bits in a PRM register (by domain) */
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static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return prm_rmw_mod_reg_bits(bits, bits, module, idx);
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}
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static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
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}
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#endif
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/*
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* Bits common to specific registers
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*
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* The 3430 register and bit names are generally used,
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* since they tend to make more sense
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*/
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/* PM_EVGENONTIM_MPU */
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/* Named PM_EVEGENONTIM_MPU on the 24XX */
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#define OMAP_ONTIMEVAL_SHIFT 0
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#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
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/* PM_EVGENOFFTIM_MPU */
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/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
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#define OMAP_OFFTIMEVAL_SHIFT 0
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#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
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/* PRM_CLKSETUP and PRCM_VOLTSETUP */
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/* Named PRCM_CLKSSETUP on the 24XX */
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#define OMAP_SETUP_TIME_SHIFT 0
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#define OMAP_SETUP_TIME_MASK (0xffff << 0)
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/* PRM_CLKSRC_CTRL */
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/* Named PRCM_CLKSRC_CTRL on the 24XX */
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#define OMAP_SYSCLKDIV_SHIFT 6
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#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
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#define OMAP_AUTOEXTCLKMODE_SHIFT 3
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#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
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#define OMAP_SYSCLKSEL_SHIFT 0
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#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
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/* PM_EVGENCTRL_MPU */
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#define OMAP_OFFLOADMODE_SHIFT 3
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#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
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#define OMAP_ONLOADMODE_SHIFT 1
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#define OMAP_ONLOADMODE_MASK (0x3 << 1)
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#define OMAP_ENABLE (1 << 0)
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/* PRM_RSTTIME */
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/* Named RM_RSTTIME_WKUP on the 24xx */
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#define OMAP_RSTTIME2_SHIFT 8
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#define OMAP_RSTTIME2_MASK (0x1f << 8)
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#define OMAP_RSTTIME1_SHIFT 0
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#define OMAP_RSTTIME1_MASK (0xff << 0)
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/* PRM_RSTCTRL */
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/* Named RM_RSTCTRL_WKUP on the 24xx */
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/* 2420 calls RST_DPLL3 'RST_DPLL' */
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#define OMAP_RST_DPLL3 (1 << 2)
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#define OMAP_RST_GS (1 << 1)
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/*
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* Bits common to module-shared registers
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*
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* Not all registers of a particular type support all of these bits -
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* check TRM if you are unsure
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*/
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/*
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* 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
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*
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* 2430: PM_PWSTST_MDM
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*
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* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
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* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
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* PM_PWSTST_NEON
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*/
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#define OMAP_INTRANSITION (1 << 20)
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/*
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* 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
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*
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* 2430: PM_PWSTST_MDM
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*
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* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
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* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
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* PM_PWSTST_NEON
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*/
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#define OMAP_POWERSTATEST_SHIFT 0
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#define OMAP_POWERSTATEST_MASK (0x3 << 0)
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/*
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* 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
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* called 'COREWKUP_RST'
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*
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* 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
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* RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
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*/
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#define OMAP_COREDOMAINWKUP_RST (1 << 3)
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/*
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* 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
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*
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* 2430: RM_RSTST_MDM
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*
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* 3430: RM_RSTST_CORE, RM_RSTST_EMU
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*/
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#define OMAP_DOMAINWKUP_RST (1 << 2)
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/*
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* 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
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* On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
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*
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* 2430: RM_RSTST_MDM
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*
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* 3430: RM_RSTST_CORE, RM_RSTST_EMU
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*/
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#define OMAP_GLOBALWARM_RST (1 << 1)
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#define OMAP_GLOBALCOLD_RST (1 << 0)
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/*
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* 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
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* 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
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*
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* 2430: PM_WKDEP_MDM
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*
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* 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
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* PM_WKDEP_PER
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*/
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#define OMAP_EN_WKUP_SHIFT 4
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#define OMAP_EN_WKUP_MASK (1 << 4)
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/*
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* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSP
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*
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* 2430: PM_PWSTCTRL_MDM
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*
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* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
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* PM_PWSTCTRL_NEON
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*/
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#define OMAP_LOGICRETSTATE (1 << 2)
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/*
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* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSP, PM_PWSTST_MPU
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*
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* 2430: PM_PWSTCTRL_MDM shared bits
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*
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* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
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* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
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* PM_PWSTCTRL_NEON shared bits
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*/
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#define OMAP_POWERSTATE_SHIFT 0
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#define OMAP_POWERSTATE_MASK (0x3 << 0)
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#endif
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