48af721540
Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
427 lines
11 KiB
Plaintext
427 lines
11 KiB
Plaintext
comment "Processor Type"
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config CPU_32
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bool
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default y
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# Select CPU types depending on the architecture selected. This selects
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# which CPUs we support in the kernel image, and the compiler instruction
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# optimiser behaviour.
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# ARM610
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config CPU_ARM610
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bool "Support ARM610 processor"
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depends on ARCH_RPC
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_COPY_V3
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select CPU_TLB_V3
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help
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The ARM610 is the successor to the ARM3 processor
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and was produced by VLSI Technology Inc.
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Say Y if you want support for the ARM610 processor.
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Otherwise, say N.
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# ARM710
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config CPU_ARM710
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bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
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default y if ARCH_CLPS7500
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_COPY_V3
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select CPU_TLB_V3
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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designed by Advanced RISC Machines Ltd. The ARM710 is the
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successor to the ARM610 processor. It was released in
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July 1994 by VLSI Technology Inc.
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Say Y if you want support for the ARM710 processor.
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Otherwise, say N.
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# ARM720T
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config CPU_ARM720T
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bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
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default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
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select CPU_32v4
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select CPU_ABRT_LV4T
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select CPU_CACHE_V4
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WT
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select CPU_TLB_V4WT
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help
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A 32-bit RISC processor with 8kByte Cache, Write Buffer and
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MMU built around an ARM7TDMI core.
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Say Y if you want support for the ARM720T processor.
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Otherwise, say N.
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# ARM920T
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config CPU_ARM920T
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bool "Support ARM920T processor" if !ARCH_S3C2410
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depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX
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default y if ARCH_S3C2410
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select CPU_32v4
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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help
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The ARM920T is licensed to be produced by numerous vendors,
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and is used in the Maverick EP9312 and the Samsung S3C2410.
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More information on the Maverick EP9312 at
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<http://linuxdevices.com/products/PD2382866068.html>.
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Say Y if you want support for the ARM920T processor.
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Otherwise, say N.
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# ARM922T
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config CPU_ARM922T
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bool "Support ARM922T processor" if ARCH_INTEGRATOR
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depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR
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default y if ARCH_CAMELOT || ARCH_LH7A40X
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select CPU_32v4
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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help
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The ARM922T is a version of the ARM920T, but with smaller
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instruction and data caches. It is used in Altera's
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Excalibur XA device family.
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Say Y if you want support for the ARM922T processor.
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Otherwise, say N.
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# ARM925T
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config CPU_ARM925T
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bool "Support ARM925T processor" if ARCH_OMAP
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depends on ARCH_OMAP1510
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default y if ARCH_OMAP1510
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select CPU_32v4
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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help
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The ARM925T is a mix between the ARM920T and ARM926T, but with
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different instruction and data caches. It is used in TI's OMAP
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device family.
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Say Y if you want support for the ARM925T processor.
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Otherwise, say N.
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# ARM926T
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config CPU_ARM926T
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bool "Support ARM926T processor" if ARCH_INTEGRATOR
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depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
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default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
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select CPU_32v5
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select CPU_ABRT_EV5TJ
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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help
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This is a variant of the ARM920. It has slightly different
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instruction sequences for cache and TLB operations. Curiously,
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there is no documentation on it at the ARM corporate website.
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Say Y if you want support for the ARM926T processor.
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Otherwise, say N.
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# ARM1020 - needs validating
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config CPU_ARM1020
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bool "Support ARM1020T (rev 0) processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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help
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The ARM1020 is the 32K cached version of the ARM10 processor,
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with an addition of a floating-point unit.
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Say Y if you want support for the ARM1020 processor.
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Otherwise, say N.
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# ARM1020E - needs validating
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config CPU_ARM1020E
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bool "Support ARM1020E processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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depends on n
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# ARM1022E
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config CPU_ARM1022
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bool "Support ARM1022E processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB # can probably do better
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select CPU_TLB_V4WBI
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help
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The ARM1022E is an implementation of the ARMv5TE architecture
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based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
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embedded trace macrocell, and a floating-point unit.
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Say Y if you want support for the ARM1022E processor.
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Otherwise, say N.
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# ARM1026EJ-S
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config CPU_ARM1026
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bool "Support ARM1026EJ-S processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB # can probably do better
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select CPU_TLB_V4WBI
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help
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The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
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based upon the ARM10 integer core.
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Say Y if you want support for the ARM1026EJ-S processor.
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Otherwise, say N.
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# SA110
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config CPU_SA110
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bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
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default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
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select CPU_32v3 if ARCH_RPC
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select CPU_32v4 if !ARCH_RPC
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WB
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help
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The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
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is available at five speeds ranging from 100 MHz to 233 MHz.
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More information is available at
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<http://developer.intel.com/design/strong/sa110.htm>.
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Say Y if you want support for the SA-110 processor.
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Otherwise, say N.
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# SA1100
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config CPU_SA1100
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bool
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depends on ARCH_SA1100
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default y
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select CPU_32v4
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_TLB_V4WB
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select CPU_MINICACHE
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# XScale
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config CPU_XSCALE
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bool
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depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
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default y
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_TLB_V4WBI
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select CPU_MINICACHE
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# ARMv6
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config CPU_V6
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bool "Support ARM V6 processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v6
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select CPU_ABRT_EV6
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select CPU_CACHE_V6
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select CPU_CACHE_VIPT
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select CPU_COPY_V6
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select CPU_TLB_V6
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# Figure out what processor architecture version we should be using.
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# This defines the compiler instruction set which depends on the machine type.
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config CPU_32v3
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bool
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config CPU_32v4
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bool
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config CPU_32v5
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bool
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config CPU_32v6
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bool
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# The abort model
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config CPU_ABRT_EV4
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bool
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config CPU_ABRT_EV4T
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bool
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config CPU_ABRT_LV4T
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bool
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config CPU_ABRT_EV5T
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bool
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config CPU_ABRT_EV5TJ
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bool
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config CPU_ABRT_EV6
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bool
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# The cache model
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config CPU_CACHE_V3
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bool
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config CPU_CACHE_V4
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bool
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config CPU_CACHE_V4WT
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bool
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config CPU_CACHE_V4WB
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bool
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config CPU_CACHE_V6
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bool
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config CPU_CACHE_VIVT
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bool
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config CPU_CACHE_VIPT
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bool
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# The copy-page model
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config CPU_COPY_V3
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bool
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config CPU_COPY_V4WT
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bool
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config CPU_COPY_V4WB
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bool
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config CPU_COPY_V6
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bool
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# This selects the TLB model
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config CPU_TLB_V3
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bool
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help
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ARM Architecture Version 3 TLB.
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config CPU_TLB_V4WT
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bool
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help
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ARM Architecture Version 4 TLB with writethrough cache.
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config CPU_TLB_V4WB
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bool
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help
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ARM Architecture Version 4 TLB with writeback cache.
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config CPU_TLB_V4WBI
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bool
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help
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ARM Architecture Version 4 TLB with writeback cache and invalidate
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instruction cache entry.
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config CPU_TLB_V6
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bool
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config CPU_MINICACHE
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bool
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help
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Processor has a minicache.
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comment "Processor Features"
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config ARM_THUMB
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bool "Support Thumb user binaries"
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depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6
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default y
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help
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Say Y if you want to include kernel support for running user space
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Thumb binaries.
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The Thumb instruction set is a compressed form of the standard ARM
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instruction set resulting in smaller binaries at the expense of
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slightly less efficient code.
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If you don't know what this all is, saying Y is a safe choice.
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config CPU_BIG_ENDIAN
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bool "Build big-endian kernel"
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depends on ARCH_SUPPORTS_BIG_ENDIAN
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help
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Say Y if you plan on running a kernel in big-endian mode.
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Note that your board must be properly built and your board
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port must properly enable any big-endian related features
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of your chipset/board/processor.
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config CPU_ICACHE_DISABLE
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bool "Disable I-Cache"
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depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
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help
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Say Y here to disable the processor instruction cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_DISABLE
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bool "Disable D-Cache"
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depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
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help
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Say Y here to disable the processor data cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
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default y if CPU_ARM925T
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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specifically require this or are unsure, say N.
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config CPU_CACHE_ROUND_ROBIN
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bool "Round robin I and D cache replacement algorithm"
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depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
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help
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Say Y here to use the predictable round-robin cache replacement
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policy. Unless you specifically require this or are unsure, say N.
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config CPU_BPREDICT_DISABLE
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bool "Disable branch prediction"
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depends on CPU_ARM1020
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help
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Say Y here to disable branch prediction. If unsure, say N.
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config HAS_TLS_REG
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bool
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depends on CPU_32v6 && !CPU_32v5 && !CPU_32v4 && !CPU_32v3
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default y
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help
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This selects support for the CP15 thread register.
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It is defined to be available on ARMv6 or later. However
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if the kernel is configured to support multiple CPUs including
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a pre-ARMv6 processors, or if a given ARMv6 processor doesn't
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implement the thread register for some reason, then access to
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this register from user space must be trapped and emulated.
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If user space is relying on the __kuser_get_tls code then
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there should not be any impact.
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